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PDF S25FL129P Fiche technique - Cypress Semiconductor

Numéro de référence S25FL129P
Description 128-Mbit 3.0 V Flash Memory
Fabricant Cypress Semiconductor 
Logo Cypress Semiconductor Logo 



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S25FL129P Datasheet, Description
S25FL129P
128-Mbit 3.0 V Flash Memory
This product is not recommended for new and current designs. For new and current designs, S25FL128S supersedes S25FL129P.
This is the factory-recommended migration path. Please refer to the S25FL128S data sheet for specifications and ordering
information.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64 KB sectors
– Top or bottom parameter block (Two 64-KB sectors broken down
into sixteen 4-KB sub-sectors each)
– Uniform 256 KB sectors (no 4-KB sub-sectors)
– 256-byte page size
– Backward compatible with the S25FL128P (uniform 256 KB
sector) device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
(for uniform 64-KB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
(for uniform 64-KB sector device only)
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory or by the
customer
CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
Process technology
– Manufactured on 0.09 µm MirrorBit® process technology
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 x 8 mm)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
– 24-ball BGA (6 x 8 mm) package, 6 x 4 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 µA (typical)
– Deep Power-Down Mode 3 µA (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00648 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 24, 2015
S25FL129P Fiche technique
S25FL129P
Contents
Distinctive Characteristics .................................................. 2
General Description ............................................................. 3
1. Block Diagram.............................................................. 5
2. Connection Diagrams.................................................. 5
3. Input/Output Descriptions........................................... 7
4. Logic Symbol ............................................................... 7
5. Ordering Information ................................................... 8
5.1 Valid Combinations ........................................................ 8
6. SPI Modes..................................................................... 9
7. Device Operations ..................................................... 10
7.1 Byte or Page Programming.......................................... 10
7.2 Quad Page Programming ............................................ 10
7.3 Dual and Quad I/O Mode ............................................. 10
7.4 Sector Erase / Bulk Erase............................................ 10
7.5 Monitoring Write Operations Using the Status Reg-
ister .............................................................................. 10
7.6 Active Power and Standby Power Modes.................... 10
7.7 Status Register ............................................................ 11
7.8 Configuration Register ................................................. 11
7.9 Data Protection Modes ................................................ 13
7.10 Hold Mode (HOLD#) .................................................... 14
7.11 Accelerated Programming Operation........................... 14
8. Sector Address Table ................................................ 15
9. Command Definitions................................................ 20
9.1 Read Data Bytes (READ) ............................................ 22
9.2 Read Data Bytes at Higher Speed (FAST_READ) ...... 23
9.3 Dual Output Read Mode (DOR)................................... 24
9.4 Quad Output Read Mode (QOR) ................................. 25
9.5 DUAL I/O High Performance Read Mode (DIOR)........ 26
9.6 Quad I/O High Performance Read Mode (QIOR) ........ 28
9.7 Read Identification (RDID) ........................................... 29
9.8 Read-ID (READ_ID)..................................................... 33
9.9 Write Enable (WREN) .................................................. 34
9.10 Write Disable (WRDI)................................................... 34
9.11 Read Status Register (RDSR) ..................................... 35
9.12 Read Configuration Register (RCR) ............................ 36
9.13 Write Registers (WRR) ................................................ 37
9.14 Page Program (PP)...................................................... 39
9.15 QUAD Page Program (QPP) ....................................... 40
9.16 Parameter Sector Erase (P4E, P8E) (only applica-
ble for the uniform 64 KB sector device)...................... 41
9.17 Sector Erase (SE) ........................................................ 42
9.18 Bulk Erase (BE) ........................................................... 43
9.19 Deep Power-Down (DP) .............................................. 44
9.20 Release from Deep Power-Down (RES)...................... 45
9.21 Clear Status Register (CLSR)...................................... 46
9.22 OTP Program (OTPP).................................................. 47
9.23 Read OTP Data Bytes (OTPR) .................................... 47
10. OTP Regions .............................................................. 48
10.1 Programming OTP Address Space.............................. 48
10.2 Reading OTP Data ....................................................... 48
10.3 Locking OTP Regions ................................................... 48
11. Power-up and Power-down........................................ 51
12. Initial Delivery State .................................................... 52
13. Program Acceleration via W#/ACC Pin..................... 52
14. Electrical Specifications............................................. 54
14.1 Absolute Maximum Ratings .......................................... 54
15. Operating Ranges ....................................................... 54
16. DC Characteristics...................................................... 55
17. Test Conditions ........................................................... 56
18. AC Characteristics...................................................... 57
18.1 Capacitance .................................................................. 58
19. Physical Dimensions .................................................. 60
19.1 SO3 016 — 16-pin Wide Plastic Small Outline
Package (300-mil Body Width) ..................................... 60
19.2 WSON 8-contact (6 x 8 mm) No-Lead Package
(WNF008) ..................................................................... 61
19.3 FAB024 — 24-ball Ball Grid Array (6 x 8 mm)
package ........................................................................ 62
19.4 FAC024 — 24-ball Ball Grid Array (6 x 8 mm)
package ........................................................................ 63
20. Revision History.......................................................... 64
Document Number: 002-00648 Rev. *I
Page 4 of 66

3 Page

S25FL129P pdf
S25FL129P
3. Input/Output Descriptions
Signal
SO/IO1
SI/IO0
SCK
CS#
HOLD#/IO3
W#/ACC/IO2
VCC
GND
I/O
I/O
I/O
Input
Input
I/O
I/O
Input
Input
Description
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes.
Serial Data Input: Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual
and Quad I/O mode.
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI
on rising edge of SCK. Triggers output on SO after the falling edge of SCK.
Chip Select: Places device in active power mode when driven low. Deselects device and
places SO at high impedance when high. After power-up, device requires a falling edge on CS#
before any command is written. Device is in standby mode when a program, erase, or Write
Status Register operation is not in progress.
Hold: Pauses any serial communication with the device without deselecting it. When driven
low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also
be driven low. Functions as an I/O pin in Quad I/O mode.
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When
driven low, prevents any program or erase command from altering the data in the protected
memory area. Functions as an I/O pin in Quad I/O mode.
Supply Voltage
Ground
4. Logic Symbol
VCC
SI/IO0
SCK
CS#
W#/ACC/IO2
HOLD#/IO3
SO/IO1
GND
Document Number: 002-00648 Rev. *I
Page 7 of 66

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