PDF S25FL127S Fiche technique - Cypress Semiconductor

Numéro de référence S25FL127S
Description 128 Mbit (16 Mbyte) 3.0V SPI Flash Memory
Fabricant Cypress Semiconductor 
Logo Cypress Semiconductor Logo 

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S25FL127S Datasheet, Description
128 Mbit (16 Mbyte)
3.0V SPI Flash Memory
CMOS 3.0 Volt Core
– 128 Mbits (16 Mbytes)
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (0.8 Mbytes/s)
– 256- or 512-byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock systems
Erase (0.5 Mbytes/s)
– Hybrid sector size option - physical set of sixteen 4-kbyte sectors
at top or bottom of address space with all remaining sectors of
64 kbytes
– Uniform sector option - always erase 256-kbyte blocks for software
compatibility with higher density and future devices.
Performance Summary
Cycling Endurance
– 100,000 Program-Erase Cycles per sector minimum
Data Retention
– 20 Year Data Retention typical
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress® 65 nm MirrorBit Technology with EclipseArchitecture
Supply Voltage: 2.7V to 3.6V
Temperature Range:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
Packages (all Pb-free)
– 8-lead SOIC (208 mil)
– 16-lead SOIC (300 mil)
– 8-contact WSON 6 x 5 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Maximum Read Rates
Fast Read
Dual Read
Quad Read
Clock Rate
Typical Program and Erase Rates
Page Programming (256-byte page buffer)
Page Programming (512-byte page buffer)
4-kbyte Physical Sector Erase (Hybrid Sector
64-kbyte Physical Sector Erase (Hybrid Sector
256-kbyte Logical Sector Erase (Uniform Sector
Current Consumption
Serial Read 50 MHz
Serial Read 108 MHz
Quad Read 108 MHz
Current (mA)
16 (max)
24 (max)
47 (max)
50 (max)
50 (max)
0.07 (typ)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98282 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 13, 2016
S25FL127S Fiche technique
1. Overview
1.1 General Description
The Cypress S25FL127S device is a flash non-volatile memory product using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to
be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous,
NOR flash memories while reducing signal count dramatically.
The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
Document Number: 001-98282 Rev. *G
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S25FL127S pdf
New Features
The FL-S family introduces several new features to SPI category memories:
Extended address for access to higher memory density.
AutoBoot for simpler access to boot code following power up.
Enhanced high performance read commands using mode bits to eliminate the overhead of SIO instructions when repeating
the same type of read command.
Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read
Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced
Sector Protection feature found in several other Cypress parallel interface NOR memory families.
1.3 Glossary
(Least Significant Bit)
(Most Significant Bit)
(Ordering Part Number)
Register Bit References
Binary Coded Decimal. A Value in which each 4-bit nibble represents a decimal numeral.
All information transferred between the host system and memory during one period while CS# is low. This
includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits,
latency cycles, or data.
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large blocks
of memory bits in parallel, making the erase operation much faster than early EEPROM.
A signal voltage level VIH or a logic level representing a binary one (1).
The 8-bit code indicating the function to be performed by a command (sometimes called an operation code or
opcode). The instruction is always the first 8 bits transferred from host system to the memory in any command.
A signal voltage level VIL or a logic level representing a binary zero (0).
Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data
Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data
No power is needed to maintain data stored in the memory.
The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration,
etc. used to select the desired device.
512 bytes or 256 bytes aligned and length group of data.
Printed Circuit Board
Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB]
Erase unit size; depending on device model and sector location this may be 4 kbytes, 64 kbytes or 256 kbytes.
An operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. When
changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of
the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data
is modified – as a single operation. The non-volatile data appears to the host system to be updated by the single
write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected
Document Number: 001-98282 Rev. *G
Page 7 of 129


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