PDF DS1077 Fiche technique - Dallas Semiconducotr

Numéro de référence DS1077
Description EconOscillator/Divider
Fabricant Dallas Semiconducotr 
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DS1077 Datasheet, Description
§ Processor-controlled or standalone solid-
state oscillator
§ Frequency changes on-the-fly
§ Dual low-jitter, synchronous fixed
frequency outputs
§ 2-wire serial interface
§ Frequency outputs 8.1kHz to 133MHz
§ ±0.5% variation over temp (+25°C to
§ ±0.5% initial tolerance
§ Nonvolatile (NV) frequency settings
§ Single 5V supply
§ No external components
§ Power-down mode
§ Synchronous output gating
Note: x denotes package option
DS1077x-133 133.333MHz to 16.2kHz
DS1077x-125 125.000MHz to 15.2kHz
DS1077x-120 120.000MHz to 14.6kHz
DS1077x-100 100.000MHz to 12.2kHz
DS1077x-66 66.666MHz to 8.1kHz
150mil SO
118mil µSOP Package
- Main Oscillator Output
- Reference Output
- Power Supply Voltage
- Ground
- Control Pin for OUT1
- Control Pin for OUT0
- 2-Wire Serial Data
SCL - 2-Wire Serial Clock
Note: XXX denotes frequency option
DS1077Z-XXX 8-Pin 150mil SO
DS1077U-XXX 8-Pin 118mil µSOP
The DS1077 is a dual-output, programmable, fixed-frequency oscillator requiring no external
components for operation. The DS1077 can be used as a processor-controlled frequency synthesizer or
as a standalone oscillator. The two synchronous output operating frequencies are user-adjustable in
submultiples of the master frequency through the use of two on-chip programmable prescalers and a
divider. The specific output frequencies chosen are stored in NV (EEPROM) memory. The DS1077
defaults to these values upon power-up.
The DS1077 features a 2-wire serial interface that allows in-circuit on-the-fly programming of the
programmable prescalers (P0 & P1) and divider (N) with the desired values being stored in NV
(EEPROM) memory. Design changes can be accommodated in-circuit on-the-fly by simply
programming different values into the device (or reprogramming previously programmed devices).
Alternatively, for fixed frequency applications, previously programmed devices can be used and no
connection to the serial interface is required. Pre-programmed devices can be ordered in customer-
requested frequencies.
The DS1077 is available in 8-pin SO or µSOP packages, allowing the generation of a clock signal
easily, economically, and using minimal board area. Chip-scale packaging is also available on request.
EconOscillator is a trademark of Dallas Semiconductor.
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DS1077 Fiche technique
A block diagram of the DS1077 is shown in Figure 1. The DS1077 consists of four major components:
1) Internal Master Oscillator, 2) Prescalers, 3) Programmable Divider, and 4) Control Registers.
The internal oscillator is factory-trimmed to provide a master frequency (Master CLK) that can be routed
directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be
routed through an additional divider (N).
The Prescaler (P0) divides the Master Clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin.
The Prescaler (P1) divides the Master Clock by 1, 2, 4, or 8, which can be routed directly to the OUT1 pin
or to the Divider (N) input, which is then routed to the OUT1 pin.
The Programmable Divider (N) divides the Prescaler Output (P1) by any number selected between 2 and
1025 to provide the Main Output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit.
The value of N is stored in the DIV register.
The Control Registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of P0, P1, & N) and modes of operation. The register values are stored in EEPROM
and therefore only need to be programmed to alter frequencies and operating modes.
Output 1 (OUT1)—This pin is the main oscillator output; its frequency is determined by the control
register settings for the prescaler P1 (mode bits 1M1 & 1M0) and divider N (DIV word).
Output 0 (OUT0)—A reference output, OUT0, is taken from the output of the reference select Mux. Its
frequency is determined by the control register settings for CTRL0 and values of Prescaler P0 (mode bits
0M1 & 0M0) (see Table 1).
Control Pin 0 (CTRL0)—A multifunctional input pin that can be selected as a MUX SELECT,
OUTPUT ENABLE and/or a POWER-DOWN. Its function is determined by the user-programmable
control register values EN0, SEL0, and PDN0 (see Table 1).
Control Pin 1 (CTRL1)—A multifunctional input pin that can be selected as a OUTPUT ENABLE
and/or a POWER-DOWN. Its function is determined by the user-programmable control register value of
PDN1 (see Table 2).
Serial Data Input/Output (SDA)—Input/Output pin for the 2-wire serial interface used for data transfer.
Serial Clock Input (SCL)—Input pin for the 2-wire serial interface used to synchronize data movement
on the serial interface.
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DS1077 pdf
EN0 (bit)
(Default EN0 = 1)
1) If EN0 = 1 and PDN0 = 0 the CTRL0 pin functions as an Output Enable for OUT0, the frequency of
the output being determined by the SEL0 bit.
2) If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, and output OUT0 will
always be enabled on power-up, its frequency being determined by the SEL0 bit.
3) If EN0 = 0 the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 1).
(Default SEL0 = 1)
1) If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX (i.e., the output
frequency of OUT0).
2) If CTRL0 = 0 the output will be the Master clock frequency.
3) If CTRL0 = 1 the output will be the output frequency of the M prescaler.
4) If either EN0 or PDN0 = 1 then SEL0 determines the frequency of OUT0 when it is enabled.
5) If SEL0 = 0 the output will be the Master clock frequency.
6) If SEL0 = 1 the output will be the output frequency of the M prescaler (see Table 1).
(Default PDN0 = 0)
1) This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the
other bits.
2) If PDN0 = 0 the function of CTRL0 is determined by the values of EN0 and SEL0.
When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all
the OUT0 circuitry is disabled even when the device is powered up for power to saving when OUT0 is
not used (see Table 1).
(Default PDN1 = 0)
1) If PDN1 = 1, CTRL1 will function as a power-down.
2) If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only (see Table 2.)
1) Both enables are “smart” and wait for the output to be low before going to Hi-Z.
2) Power-down sequence first disables both outputs before powering down the device.
3) On power-up the outputs are disabled until the clock has stabilized (~8000 cycles).
4) In power-down mode, the device cannot be programmed.
5) A power-down command must persist for at least two cycles of the lowest output frequency plus 10ms.
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