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PDF 74LV244 Fiche technique - NXP

Numéro de référence 74LV244
Description Octal buffer/line driver
Fabricant NXP 
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74LV244 Datasheet, Description
74LV244
Octal buffer/line driver; 3-state
Rev. 4 — 1 March 2016
Product data sheet
1. General description
The 74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible
with 74HC244 and 74HCT244.
The 74LV244 is an octal non-inverting buffer/line driver with 3-state outputs. The output
enable inputs 1OE and 2OE control the 3-state outputs. A HIGH on nOE causes the
outputs to assume a high impedance OFF-state. The 74LV244 is identical to the 74LV240
but has non-inverting outputs.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 C
Complies with JEDEC standard no. 7A
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74LV244D
40 C to +125 C
74LV244DB 40 C to +125 C
74LV244PW 40 C to +125 C
Name Description
Version
SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74LV244 Fiche technique
NXP Semiconductors
74LV244
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
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5.2 Pin description
Table 2. Pin description
Symbol
1OE, 2OE
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2A0, 2A1, 2A2, 2A3
1Y0, 1Y1, 1Y2, 1Y3
VCC
Pin
1, 19
2, 4, 6, 8
3, 5, 7, 9
10
17, 15, 13, 11
18, 16, 14, 12
20
6. Functional description
Description
output enable input (active LOW)
data input
bus output
ground (0 V)
data input
bus output
supply voltage
Table 3.
Input
nOE
L
L
H
Function table[1]
nAn
L
H
X
Output
nYn
L
H
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LV244
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 1 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LV244 pdf
NXP Semiconductors
74LV244
Octal buffer/line driver; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 7
Symbol Parameter
Conditions
tpd
propagation delay 1An to 1Yn; 2An to 2Yn;
[2]
see Figure 5
ten enable time
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
1OE to 1Yn; 2OE to 2Yn;
see Figure 6
[2]
tdis disable time
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1OE to 1Yn; 2OE to 2Yn;
see Figure 6
[2]
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD power dissipation VI = GND to VCC; VCC = 3.3 V [3]
capacitance
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max Min Max
- 50
-
- 17 24 -
- 13 17 -
- 9 14 -
-8-
-
- - 12 -
- ns
31 ns
23 ns
18 ns
- ns
15 ns
- 65 -
-
- 22 39 -
- 16 29 -
- 12 23 -
- - 19 -
- ns
49 ns
36 ns
29 ns
24 ns
- 60
-
- 22 34 -
- 17 24 -
- 13 21 -
- - 16 -
- 35 -
-
- ns
43 ns
32 ns
26 ns
19 ns
- ns
[1] Unless otherwise stated, all typical values are measured at Tamb = 25 C and nominal VCC.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
74LV244
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 1 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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