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PDF 25C080 Fiche technique - Microchip Technology

Numéro de référence 25C080
Description 8K SPI Bus Serial EEPROM
Fabricant Microchip Technology 
Logo Microchip Technology Logo 

22 Pages
		

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25C080 Datasheet, Description
Not recommended for new designs –
Please use 25AA080A/B or 25LC080A/B.
25AA080/25LC080/25C080
8K SPI Bus Serial EEPROM
Device Selection Table
Part
Number
25AA080
25LC080
25C080
VCC
Range
1.8-5.5V
2.5-5.5V
4.5-5.5V
Max. Clock
Frequency
1 MHz
2 MHz
3 MHz
Temp.
Ranges
I
I
I,E
Features:
• Low-power CMOS technology:
- Write current: 3 mA maximum
- Read current: 500 A typical
- Standby current: 500 nA typical
• 1024 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed erase and write cycles
• Block write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability:
- Endurance: 1 M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP and SOIC (150 mil)
• Temperature ranges supported:
- Industrial (I):
-40C to +85C
- Automotive (E) (25C080): -40°C to +125°C
Description:
The Microchip Technology Inc. 25AA080/25LC080/
25C080 (25XX080*) are 8 Kbit Serial Electrically
Erasable PROMs. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
Package Types
PDIP/SOIC
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
Block Diagram
Status
Register
HV Generator
I/O Control
Logic
Memory
Control
Logic
X
Dec
EEPROM
Array
Page Latches
SI
SO
CS
SCK
HOLD
WP
VCC
VSS
Y Decoder
Sense Amp.
R/W Control
1997-2012 Microchip Technology Inc.
DS21230E-page 1
25C080 Fiche technique
25AA080/25LC080/25C080
1.2 AC Characteristics
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 only)
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1 FCLK Clock Frequency
— 3 MHz VCC = 4.5V to 5.5V
— 2 MHz VCC = 2.5V to 4.5V
— 1 MHz VCC = 1.8V to 2.5V
2 TCSS CS Setup Time
100 — ns VCC = 4.5V to 5.5V
250 — ns VCC = 2.5V to 4.5V
500 — ns VCC = 1.8V to 2.5V
3 TCSH CS Hold Time
150 — ns VCC = 4.5V to 5.5V
250 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
4 TCSD CS Disable Time
500 — ns —
5 Tsu Data Setup Time
30 — ns VCC = 4.5V to 5.5V
50 — ns VCC = 2.5V to 4.5V
50 — ns VCC = 1.8V to 2.5V
6 THD Data Hold Time
50 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
100 — ns VCC = 1.8V to 2.5V
7 TR
CLK Rise Time
— 2 s (Note 1)
8 TF
CLK Fall Time
— 2 s (Note 1)
9 THI Clock High Time
150 — ns VCC = 4.5V to 5.5V
230 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
10 TLO Clock Low Time
150 — ns VCC = 4.5V to 5.5V
230 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
11 TCLD Clock Delay Time
50 — ns —
12 TCLE Clock Enable Time
50 — ns —
13 TV
Output Valid from Clock Low
150 ns VCC = 4.5V to 5.5V
230 ns VCC = 2.5V to 4.5V
475 ns VCC = 1.8V to 2.5V
14 THO Output Hold Time
0 — ns (Note 1)
15 TDIS Output Disable Time
— 200 ns VCC = 4.5V to 5.5V (Note 1)
— 250 ns VCC = 2.5V to 4.5V (Note 1)
— 500 ns VCC = 1.8V to 2.5V (Note 1)
16 THS HOLD Setup Time
100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
200 — ns VCC = 1.8V to 2.5V
17 THH HOLD Hold Time
100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
200 — ns VCC = 1.8V to 2.5V
18 THZ HOLD Low to Output High-Z
100
150
200
— ns VCC = 4.5V to 5.5V (Note 1)
— ns VCC = 2.5V to 4.5V (Note 1)
— ns VCC = 1.8V to 2.5V (Note 1)
19 THV HOLD High to Output Valid
100
150
200
— ns VCC = 4.5V to 5.5V
— ns VCC = 2.5V to 4.5V
— ns VCC = 1.8V to 2.5V
20 TWC Internal Write Cycle Time
5 ms —
21 —
Endurance
1M — E/W (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.
1997-2012 Microchip Technology Inc.
DS21230E-page 3

3 Page

25C080 pdf
25AA080/25LC080/25C080
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
PDIP SOIC
Function
CS
SO
WP
Vss
SI
SCK
HOLD
Vcc
1
2
3
4
5
6
7
8
1 Chip Select Input
2 Serial Data Output
3 Write-Protect Pin
4 Ground
5 Serial Data Input
6 Serial Clock Input
7 Hold Input
8 Supply Voltage
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX080.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the nonvolatile bits in the Status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP going low will have no effect on the write.
The WP pin function is blocked when the WPEN bit in
the Status register is low. This allows the user to install
the 25XX080 in a system with WP pin grounded and
still be able to write to the Status register. The WP pin
functions will be enabled when the WPEN bit is set
high.
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX080. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX080 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX080 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume. Lowering the HOLD line at any
time will tri-state the SO line.
DS21230E-page 6
1997-2012 Microchip Technology Inc.

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