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PDF IN25AA040D Fiche technique - Integral

Numéro de référence IN25AA040D
Description NONVOLATILE ELECTRICALLY ERASABLE PROM
Fabricant Integral 
Logo Integral Logo 

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IN25AA040D Datasheet, Description
IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
NONVOLATILE ELECTRICALLY ERASABLE PROM WITH SERIAL
PERIPHERAL INTERFACE (SPI).
DESCRIPTION
The IN25АА020N/D are a 2K(256x8) serial Electrically Erasable PROM with SPI interface.
*The IN25АА040N/D are a 4K (512x8) serial Electrically Erasable PROM with SPI interface (SPI).
The ICs is purposed for reading, writing & nonvolatile data storage in electronic units with SPI interface. ICs
are realized in SO-8 (MS-012АA) and DIP-8 (MS-001BA)
FEATURES
- Data capacity, QINF:
for IN25АА020N, IN25АА020D
for IN25АА040N, IN25АА040D
2048 bit,
4096 bit;
- Maximum clock frequency, fC:
for 4,5 V UCC 5,5 V
for 2,5 V UCC 5,5 V
for 1,8 V UCC 5,5 V
- Maximum stand-by current, ICC:
for UCC = 5,5 V, UIL = 0 V, UIH = UCC
for UCC = 2,5 V, UIL = 0 V, UIH = UCC
3 MHz;
2 MHz;
1 MHz;
5,0 uA
1,0 uA;
- Maximum read current, IOCCR :
for UCC = 5,5 В, fC = 3,0 МГц, SO pin is not loaded .…1,0 mA,
for UCC = 2,5 В, fC = 2,0 МГц, SO pin is not loaded …..0,5 mA;
- Maximum write current, IOCCW :
for UCC = 5,5 V
5,0 mA;
for UCC = 2,5 V
3,0 mA;
- Byte & page (16 bytes) data write modes are available;
- Endurance NE/W, …...1000000 cycles;
- Write protection block protect none, 1/4, 1/2, or all of storage
array;
- Power on/off data protection circuitry;
- Supply voltage UCC 1,8 … 5,5 V;
- Temperature range -40 … +85°C.
- 100 years non-volatile data retention time
N SUFFIX
DIP
8
1 D SUFFIX
8 SOIC
1
Pin
Name
CS
SO
WP
GND
SI
SCK
HOLD
VCC
Function
Chip Select
Serial Data Output
Write protection
Ground
Serial Data Input
Clock Input
Hold input *
Power Supply
PIN FUNCTIONS
CS 01
SO 02
WP 03
GND 04
08 Vcc
07 HOLD
06 SCK
05 SI
Ver.00/11.07.2008
1 IN25AA020(040)-TSe.doc
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IN25AA040D Fiche technique
IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Electric Parameters ( -40oCTA85oC
Parameter, unit
Symbol
Mode
Low level output voltage, V
High level output voltage, V
Low level input leakage current, uA
UOL 2,5 V UCC 5,5 V
IOL = 2,1 mA
1,8 V UCC 2,5 V
IOL = 1,0 mA
UOH UCC = 1,8 V
IOH = -400 uA
UCC = 5,5 V
IOH = -400 uA
IILL UI = 0 V
High level input leakage current, uA IILH UI = 5,5V
Low level output leakage current,
uA
IOLL UI = 0 V
High level output leakage current,
uA
IOLH UI = 5,5V
Consumption current, uA
Consumption current (Operating
Read), uA
ICC
IOCC R
Ucc = 5,5 V, UIL = 0 V
UIH = Ucc
Ucc = 2,5 V, UIL = 0 V
UIH = Ucc
Ucc = 5,5 V, fC = 3 MHz
SO pin is not loaded
Ucc = 2,5 V, fC = 2 MHz
SO pin is not loaded
Consumption current (Operating
Write), uA
IOCC W
Ucc = 5,5 V, fC = 3 MHz
Ucc = 2,5 V, fC = 2 MHz
Data access time on SCK tran-
sition to low level, ns
tV
4,5 V UCC 5,5 V,
fC 3 MHz
2,5 V UCC < 4,5 V,
fC 2 MHz
1,8 V UCC < 2,5 V,
fC 1 MHz
4,5 V UCC 5,5 V,
fC 3 MHz
Output disable time on CS
high, ns
tDIS
2,5 V UCC < 4,5 V,
fC 2 MHz
1,8 V UCC < 2,5 V,
fC 1 MHz
4,5 V UCC 5,5 V,
fC 3 MHz
Output disable time on HOLD
low, ns
tHZ
2,5 V UCC < 4,5 V,
fC 2 MHz
1,8 V UCC < 2,5 V,
fC 1 MHz
4,5 V UCC 5,5 V,
fC 3 MHz
Output enable time on HOLD
high, ns
tHV
2,5 V UCC < 4,5 V,
fC 2 MHz
Write/Erase cycle, ms
Program/erase cycles
tCY
NE/W
1,8 V UCC < 2,5 V,
fC 1 MHz
UCC = 4,5 V, fC = 3 MHz
Ucc = 5,0 V
Min
-
1,3
5,0
-
-
-
-
-
-
-
-
100
150
200
100
150
200
1000000
Max
0,4
0,2
-10,0
10,0
-10,0
10,0
5,0
1,0
1,0
0,5
5,0
3,0
150
230
475
200
250
500
-
-
-
-
-
-
5
TA, °С
25 ± 10;
-45; 85
25±10
–40
85
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3 Page

IN25AA040D pdf
IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Byte write sequence
CS
SCK
t WC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
Lower address byte
Data byte
SI 0 0 0 0 A8 0 1 0 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0
SO High-Z
Read status register sequence
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Instruction
SI 0 0 0 0 0 1 0 1
Status register
High-Z
output data
SO 7 6 5 4 3 2 1 0
The RDSR (read status register) instruction provides access to the status register. The status register may
be read at any time, even during a write cycle.
The 0th bit - WIP bit (Write-In-Process) of the status register indicates whether the IC is busy with a write
operation. When set to a ‘1’ a write is in progress, when set to a ‘0’ no write is in progress. This bit is read
only.
The 1st bit - WEL bit (Write Enable Latch) of the status register indicates the status
of the write enable latch. When set to a ‘1’ the latch allows writes to the array, when set to a ‘0’ the latch pro-
hibits writes to the array. This bit is read only.
The 2nd & 3rd bits - BP0 and BP1 bits (Block Protection) indicate which blocks are currently write protected.
These bits are set by the user issuing the WRSR instruction.
The SCK is used to synchronize the communication between a master and the IC. Instructions, addresses,
or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is
updated after the falling edge of the clock input.
Ver.00/11.07.2008
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