DataSheet.fr

PDF AR9287 Fiche technique - Atheros

Numéro de référence AR9287
Description Single-Chip 2x2 MIMO MAC/BB/Radio
Fabricant Atheros 
Logo Atheros Logo 



30 Pages
		

No Preview Available !

AR9287 Datasheet, Description
Data Sheet
February 2010
AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio with PCIE
Interface for 802.11n 2.4 GHz WLANs
General Description
The Atheros AR9287 is a highly integrated
single-chip solution for 2.4 GHz 802.11n-ready
WLANs to enable high-performance 2x2 MIMO
configurations for applications demanding
robust link quality and maximum throughput
and range. The AR9287 integrates a multi-
protocol MAC, baseband processor, analog-to-
digital and digital-to-analog (ADC/DAC)
converters, 2x2 MIMO radio transceiver
including LNA, PA, and RF switch, and PCI
Express interface in an all-CMOS device for low
power and small form factor applications.
The AR9287 implements half-duplex OFDM,
CCK, and DSSS baseband processing, supporting
up to 150 Mbps for 20 MHz and 300 Mbps for
40 MHz channel operations respectively, and
IEEE 802.11b/g data rates. Additional features
include signal detection, automatic gain control,
frequency offset estimation, symbol timing, and
channel estimation. The AR9287 MAC supports
the 802.11 wireless MAC protocol, 802.11i
security, receive and transmit filtering, error
recovery, and quality of service (QoS).
The AR9287 supports two simultaneous traffic
streams using up to two integrated transmit
chains and receive chains for high throughput
and range performance. Transmit chains combine
baseband in-phase (I) and quadrature (Q) signals,
convert them to the desired frequency, and drive
the RF signal to multiple antennas. Receive
chains convert RF signal to baseband I and Q
outputs. The frequency synthesizer supports
one-MHz steps to match frequencies defined by
IEEE 802.11b/g/n specifications.
The AR9287 supports frame data transfer to and
from the host using a PCIE interface providing
interrupt generation and reporting, power save,
and status reporting. Other external interfaces
include serial EEPROM and GPIOs. The AR9287
operates with standard legacy 802.11b/g devices.
Features
All-CMOS MIMO solution interoperable with
IEEE 802.11b/g/n WLANs
2x2 MIMO technology improves effective
throughput and range over existing
802.11b/g products
Integrated LNAs, PAs, and RF switches
eliminate the need for external front-end
modules
Supports spatial multiplexing, cyclic-delay
diversity (CDD), and maximal ratio
combining (MRC)
2.4 GHz WLAN MAC/BB processing
BPSK, QPSK, 16 QAM, 64 QAM, DBPSK,
DQPSK, and CCK modulation schemes
Data rates of up to 150 Mbps for 20 MHz
channels and 300 Mbps for 40 MHz channels
Wireless multimedia enhancements for QoS
802.11e-compatible bursting
Support for IEEE 802.11e, h, and i standards
WEP, TKIP, and AES hardware encryption
20 and 40 MHz channelization
PCIE 1.1 compliant
Support for 2–3 wire Bluetooth coexistence
Reduced (short) guard interval
Frame aggregation
Block ACK
IEEE 1149.1 standard test access port and
boundary scan architecture supported
9 mm x 9 mm 76-pin LPCC package
AR9287 System Block Diagram
© 2009-2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-Nav®,
Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, Ethos™,
Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1
AR9287 Fiche technique
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR9287 System Block Diagram .................... 1
1 Pin Descriptions ............................ 1
2 Functional Description ................. 7
2.1 Overview ................................................... 7
2.1.1 Configuration Block ..................... 7
2.1.2 AR9287 Address MAP ................. 7
2.1.3 Serial EEPROM Interface ............. 8
2.1.4 EEPROM Auto-Sizing Mechanism
8
2.1.5 EEPROM Read/Write Protection
Mechanism ..................................... 8
2.2 Reset ........................................................... 8
2.3 GPIO .......................................................... 8
2.4 LED ............................................................ 8
2.5 PCI Express Host Interface ..................... 9
2.5.1 PCI Express Registers .................. 9
2.6 Signal Description .................................... 9
2.7 Host Interface Unit Interrupts ................ 9
3 Medium Access Control (MAC) 11
3.1 Overview ................................................. 11
3.2 Descriptor ................................................ 11
3.3 Descriptor Format .................................. 12
3.4 Queue Control Unit (QCU) .................. 28
3.4.1 DCF Control Unit (DCU) ........... 28
3.5 Protocol Control Unit (PCU) ................ 28
4 Digital PHY Block ....................... 29
4.1 Overview ................................................. 29
4.2 802.11n (MIMO) Mode .......................... 29
4.2.1 Transmitter (Tx) .......................... 29
4.2.2 Receiver (Rx) ............................... 29
4.3 802.11b/g Legacy Mode ........................ 30
4.3.1 Transmitter .................................. 30
4.3.2 Receiver ........................................ 30
5 Radio Block .................................. 31
5.1 Receiver (Rx) Block ................................ 31
5.2 Transmitter (Tx) Block .......................... 32
5.3 Synthesizer (SYNTH) Block ................. 33
5.4 Bias/Control (BIAS) Block ................... 33
6 LDO Circuit Recommendation .35
6.1 PNP Transistor ....................................... 35
7 Register Descriptions ..................37
7.1 PCI Express Configuration Space
Registers 37
7.1.1 Vendor ID (VENDOR_ID) ........ 38
7.1.2 Device ID (DEVICE_ID) ............ 38
7.1.3 Command (COMMAND) ......... 39
7.1.4 Status (STATUS) ......................... 40
7.1.5 Revision ID (REVISION_ID) ..... 40
7.1.6 Class Code (CLASS_CODE) ..... 41
7.1.7 Cache Line Size (CACHE_SZ) .. 41
7.1.8 Latency Timer (LATENCY_TMR)
41
7.1.9 Header Type (HDR_TYPE) ....... 41
7.1.10 ....Base Address (BASE_ADDR) 41
7.1.11 Subsystem Vendor ID
(SSYS_VEND_ID) ....................... 42
7.1.12 ........... Subsystem ID (SSYS_ID) 42
7.1.13 Capabilities Pointer (CAP_PTR) 42
7.1.14 Interrupt Line (INT_LINE) ....... 42
7.1.15 ............ Interrupt Pin (INT_PIN) 42
7.1.16 Power Management Capability 43
7.1.17 Power Management Status/
Control ......................................... 44
7.1.18 Message Capability ID (CAP_ID)
44
7.1.19 Message Capability Next Pointer
(NXT_PTR) .................................. 44
7.1.20 Message Control ......................... 45
7.1.21 Message Address ....................... 46
7.1.22 Message Data ............................. 46
7.1.23 PCI Express Capabilities List ... 46
7.1.24 PCI Express Capabilities ........... 47
7.1.25 Link Capabilities ......................... 47
7.1.26 Link Control ................................ 48
7.2 AR9287 Internal Register Descriptions 48
7.2.1 General DMA and Rx-Related
Registers ....................................... 49
7.2.2 Beacon Handling ........................ 68
7.2.3 QCU Registers ............................. 70
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 1
February 2010 1

3 Page

AR9287 pdf
Figure 1-1. LPCC Package Pin Assignments
2 • AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs
2 February 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

6페이지



Constitution30 Pages
Télécharger[ AR9287.PDF ]

Liens de partage


Fiche technique recommandé

RéférenceDescriptionFabricant
AR9280Single-Chip 2x2 MIMO MAC/BB/RadioAtheros
Atheros
AR9287Single-Chip 2x2 MIMO MAC/BB/RadioAtheros
Atheros

RéférenceDescriptionFabricant
H6060Monolithic low-power CMOS device combining a programmable timerEM Microelectronic - MARIN SA
EM Microelectronic - MARIN SA
IT8772EHighly integrated Super I/O using the Low Pin Count InterfaceITE
ITE

Un datasheet est un document fourni par le constructeur du composant, où figurent toutes les données techniques sur le produit: puissance dissipée, courant maximal, tension de seuil, tension de claquage, température de stockage, etc.


www.DataSheet.fr    |   2019   |  Contactez-nous    |   Recherche