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Numéro de référence NB3N853531E
Description 3.3V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
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NB3N853531E Datasheet, Description
NB3N853531E
3.3 V Xtal or
LVTTL/LVCMOS Input 2:1
MUX to 1:4 LVPECL Fanout
Buffer
Description
The NB3N853531E is a low skew 3.3 V supply 1:4 clock
distribution fanout buffer. An input MUX selects either a
Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by
using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with
LVCMOS / LVTTL levels.
The single ended CLK input is translated to four LVPECL Outputs.
Using the crystal input, the NB3N853531E can be a Clock Generator.
A CLK_EN pin can enable or disable the outputs synchronously to
eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable
outputs, LOW to disable outputs).
Features
Four Differential 3.3 V LVPECL Outputs
Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max)
Device to Device Skew 200 ps (Max)
Propagation Delay 1.8 ns (Max)
Operating Range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 0.053 ps (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (40°C to 85°C)
PbFree TSSOP20 Package
Ambient Operating Temperature Range 40°C to +85°C
These are PbFree Devices
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MARKING
DIAGRAM
TSSOP20
DT SUFFIX
CASE 948E
NB3N
531E
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
CLK_EN
Pullup
CLK
Pulldown
XTAL_IN
XTAL_OUT
OSC
CLK_SEL
Pulldown
0
1
D
Q
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
© Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. 6
1
Publication Order Number:
NB3N853531E/D
NB3N853531E Fiche technique
NB3N853531E
CLK
CLK_EN
Q[0:3]
Q[0:3]
Disabled
Enabled
Figure 3. CLK_EN Timing Diagram
Table 3. ATTRIBUTES (Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
Cin Input Capacitance
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
50 kW
50 kW
4 pF
> 2 kV
> 200 V
Level 1
UL 94 V0 @ 0.125 in
28 to 34
333 Devices
Table 4. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
VCC Supply Voltage
Vin Input Voltage
Iout Output Current
Continuous
Surge
4.6
0.5 v VI v VCC + 0.5
50
100
V
V
mA
TA Operating Temperature Range, Industrial
Tstg Storage Temperature Range
θJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
SingleLayer
PCB (700 mm2,
2 oz)
40 to v +85
65 to +150
128
°C
°C
°C/W
200 lfpm
MultiLayer
PCB (700 mm2,
2 oz)
94
θJC Thermal Resistance (JunctiontoCase)
(Note 4)
TSSOP20
23 to 41
°C/W
Tsol Wave Solder
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
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NB3N853531E pdf
NB3N853531E
NB3N853531E
Source Generator
Figure 6. For 155.52 MHz Carrier, the NB3N853531E Additive Phase Noise (dBc/Hz) verses SSB Offset Frequency
(Hz) Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 88.1 fs RMS. The E8663B Source Generator
Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where tJIT = /(tJIToutput)2 (tJITinput)2 = 53 fs
Application Crystal Input Interface
Figure 7 shows the NB3N853531E device crystal
oscillator interface using a typical parallel resonant crystal.
A parallel crystal with loading capacitance CL = 18 pF could
use Series Load Caps C1 = 32 pF and C2 = 32 pF as nominal
values, after subtracting a typical 4 pF of stray cap per line.
The frequency accuracy and duty cycle skew can be fine
tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
32 pF
32 pF
C1 XTAL_IN/CLK
X1 18 pF
Parallel Resonant
Crystal
C2 R1*
XTAL_OUT
Figure 7. NB3N853531E Crystal Oscillator Interface
*R1 is optional. Assuming 4 pF stray cap per pin.
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