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PDF 5H11G Fiche technique ( Data sheet )

Numéro de référence 5H11G
Description Complementary Power Transistors
Fabricant ETC 
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5H11G Datasheet, Description
4H11G(NPN)
5H11G(PNP)
Preferred Device
Complementary Power
Transistors
DPAK For Surface Mount Applications
Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
Features
Pb−Free Packages are Available
Lead Formed for Surface Mount Application in Plastic Sleeves
(No Suffix)
Straight Lead Version in Plastic Sleeves (“−1” Suffix)
Lead Formed Version in 16 mm Tape and Reel for Surface Mount
(“T4” Suffix)
Electrically Similar to Popular D44H/D45H Series
Low Collector Emitter Saturation Voltage −
VCE(sat) = 1.0 Volt Max @ 8.0 Amperes
Fast Switching Speeds
Complementary Pairs Simplifies Designs
Epoxy Meets UL 94, V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
MAXIMUM RATINGS
Rating
Collector−Emitter Voltage
Emitter−Base Voltage
Collector Current − Continuous
Peak
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation* @ TA = 25°C
Derate above 25°C
Operating and Storage Junction Temperature
Range
Symbol
VCEO
VEB
IC
PD
PD
TJ, Tstg
Max
80
5
8
16
20
0.16
1.75
0.014
−55 to
+ 150
Unit
Vdc
Vdc
Adc
W
W/°C
W
W/°C
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
THERMAL CHARACTERISTICS
Characteristic
Symbol Max Unit
Thermal Resistance, Junction−to−Case
RqJC
6.25 °C/W
Thermal Resistance, Junction−to−Ambient*
RqJA
71.4 °C/W
Lead Temperature for Soldering
TL 260 °C
*These ratings are applicable when surface mounted on the minimum pad sizes
recommended.
SILICON
POWER TRANSISTORS
8 AMPERES
80 VOLTS
20 WATTS
MARKING
DIAGRAMS
12
3
4
DPAK
CASE 369C
STYLE 1
YWW
J4
xH11
1
2
3
4
DPAK−3
CASE 369D
STYLE 1
Y = Year
WW = Work Week
x = 4 or 5
YWW
J4
xH11
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5H11G Fiche technique
4H11 (NPN) 5H11 (PNP)
1
0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
0.1 0.05
0.07
0.05 0.02
0.03 0.01
0.02 SINGLE PULSE
0.01
0.01 0.02 0.03 0.05 0.1
RqJC(t) = r(t) RqJC
RqJC = 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) qJC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
0.2 0.3 0.5 1
2 3 5 10 20 30 50
t, TIME (ms)
Figure 1. Thermal Response
100 200 300 500 1 k
20
10
5
3
2
1
0.5
0.3
0.1
0.05
0.02
1
500 ms 100 ms
dc 5 ms
1 ms
THERMAL LIMIT @ TC = 25°C
WIRE BOND LIMIT
3 5 7 10
20 30 50 70 100
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 2. Maximum Forward Bias
Safe Operating Area
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I C − V CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 2 is based on T J(pk) = 150 _C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T J(pk)
v 150_C. T J(pk) may be calculated from the data in
Figure 1. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
TA TC
2.5 25
2 20
1.5 15
1 10
0.5 5
00
25
TC
TA
SURFACE
MOUNT
50 75 100 125
T, TEMPERATURE (°C)
Figure 3. Power Derating
150
4

3 Page

5H11G pdf
4H11 (NPN) 5H11 (PNP)
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
S
−T−
SEATING
PLANE
B
R
4
123
A
K
C
E
F
G
J
D 3 PL
0.13 (0.005) M T
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
G 0.090 BSC
2.29 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
7

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