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PDF STV3208 Fiche technique - ST Microelectronics

Numéro de référence STV3208
Description 8 x 8 DISCRETE COSINE TRANSFORM
Fabricant ST Microelectronics 
Logo ST Microelectronics Logo 

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STV3208 Datasheet, Description
STV3208
8 x 8 DISCRETE COSINE TRANSFORM (DCT)
. 0 TO 27MHz PIXEL RATE IN SINGLE
PRECISION MODE,
. 0 TO 20 MHz PIXEL RATE IN DOUBLE
PRECISION MODE
. FORWARD AND INVERSE 8 x 8 TRANS-
FORM
. 9-BIT TWO’S COMPLEMENT PIXEL FORMAT
. 12-BIT TWO’S COMPLEMENT COEFFICIENT
FORMAT
. OPTIMIZED ACCURACY FOR 8-BIT TWO’S
COMPLEMENT PIXEL FORMAT
. SELECTABLE SCANNING OF COEFFICIENT
BLOCKS
. FULLY TTL AND CMOS COMPATIBLE
. CMOS TECHNOLOGY
. SINGLE +5 VOLT POWER SUPPLY
. MAXIMUM POWER DISSIPATION : 750mW
AT 27MHz
DIP40
(Plastic Package)
DESCRIPTION
The STV3208 is a dedicated circuit for the 8 x 8
discrete cosine transform(DCT) computation.Two-
dimensional forward DCT (FDCT) or inverse DCT
(IDCT) is performed for 8 x 8 block sizes and a pixel
rate up to 27MHz. The circuit architecture is fully
bidirectional with 9-bit magnitude pixel data bus
and a 12-bit magnitude coefficient data bus pro-
grammed as input or output depending on the
selection of FDCT or IDCT.
Pixel Bus
Coefficient Bus
FDCT
Input
Output
IDCT
Output
Input
Data Format
9-bit 2’s
Complement
12-bit 2’s
Complement
For the forward transform, the input pixels are
coded on 9-bit 2’s complement and the output
coefficients are coded on 12-bit 2’s complement.
For the inverse transform, the data format is iden-
tical with the coefficients used as input and the
pixels used as output.
Two operating modes are provided : single preci-
sion mode at a pixel rate up to 27 MHz, and double
precision mode at a pixel rate up to 20 MHz.
PQFP44
(Plastic Package)
ORDER CODES
Part
Number
STV3200CP
STV3200CV
Temperature
Range
0 to 70oC
0 to 70oC
Package
DIP 40
PQFP44
July 1992
1/17
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STV3208 Fiche technique
FUNCTIONAL BLOCK DIAGRAM
STV3208
FUNCTIONAL DESCRIPTION
1. EQUATIONS
Figure 1
M Lines
Pixel Data
Block
FDCT
IDCT
Coeff.
Data
Block
N Lines
N columns
M columns
The STV3208performs8 x 8 two dimensional Discrete Cosine Transform according to the following formula:
Equations for 9-bit PIXEL DATA (PR pin set to low) :
FORWARD TRANSFORM EQUATION :
∑ ∑F( u , v ) = Round

1
4
C(u)
C(v)
i
7
=0
7
j=0
D( i , j )
cos (2i + 1) u π
16
cos
(2
j
+ 1)
16
v
π
3/17
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3 Page

STV3208 pdf
STV3208
Figure 4
4. BLOCK FLOW
Depending on the application, blocks may be en-
tered in different way.
Latent period :
The latent period between input data and corre-
sponding output results is 167 clock cycles (if FDCT
is selected)or 163 clock cycles (if IDCT is selected)
in single precision mode (S/D pin set to 1). This
means that the first data of the resulting block is
provided 137 clock cycles (if FDCT is selected) or
135 clock cycles (if IDCT is selected) in double
precision mode (S/D pin set
to 0).
Latency
S/D = 1
Single Precision
S/D = 0
Double Precision
Forward DCT
167 Cycles
137 Cycles
Inverse DCT
163 Cycles
135 Cycles
Synchronization signals :
An input block synchronization signal must be pro-
vided. The input pin for this signal is DSYNC if
FDCT is selected and FSYNC if IDCT is se-
lected.This signal is active low and must not be
active more than one clock cycle and during the
Figure 5
first clock cycle after power-up.This signal must be
active with the first data of each input block or group
of blocks.
An output block synchronization signal is provided.
The output pin for this signal is FSYNC if FDCT is
selected and DSYNC if IDCT is selected. This
signal is active with the first data of each output
block or group of blocks.
The output synchronization signal is equal to the
input synchronization signal delayed from the la-
tent period (see Figure 5).
CONTINUOUS BLOCK FLOW
Inputs data are fed continously with one new item
data at each clock cycle and output data is provided
continously with one new result data item at each
clock cycle.
The input synchronization signal can be provided
for each input block. In this case the output syn-
chronization pulse is provided for each output block
(Figure 6). An other way is to provide a synchroni-
zation pulse only for the first block of a group of
blocks. In this case, only one synchronizationpulse
is provided for the first output block (Figure 7).
6/17
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