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PDF P60N03L Fiche technique - Fairchild Semiconductor

Numéro de référence P60N03L
Description EQP60N03L
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 



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P60N03L Datasheet, Description
FQP60N03L
30V LOGIC N-Channel MOSFET
May 2001
QFET TM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as DC/DC
converters, high efficiency switching for power
management in portable and battery operated products.
Features
• 60A, 30V. RDS(on) = 0.0135@VGS = 10 V
• Low gate charge ( typical 18.5 nC)
• Low Crss ( typical 155 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
GD S
TO-220
FQP Series
http://www.DataSheet4U.net/
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
D
!
"
!"
G!
"
"
!
S
FQP60N03L
30
60
42.5
240
± 20
220
60
10.0
7.0
100
0.67
-55 to +175
300
Typ Max
-- 1.50
0.5 --
-- 62.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
datasheet pdf - http://www.DataSheet4U.net/
P60N03L Fiche technique
Typical Characteristics
VGS
Top : 10.0 V
8.0 V
6.0 V
102 5.0 V
4.5 V
4.0 V
3.5 V
Bottom: 3.0V
101
Notes :
1. 250μ s Pulse Test
2. TC = 25
10-1 100 101
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
102
101
175
25
-55
Notes :
1.
2.
V25DS0μ=s15PVulse
Test
100
0 2 4 6 8 10
V , Gate-Source Voltage [V]
GS
Figure 2. Transfer Characteristics
40
30
V = 5V
GS
20
VGS = 10V
10
Note : TJ = 25
0
0 40 80 120 160 200 240
ID, Drain Current [A]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
3000
2500
2000
1500
C
oss
C
iss
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
C =C
rss gd
Notes :
1. VGS = 0 V
2. f =1 MHz
1000
500
C
rss
0
10-1 100 101
V , Drain-Source Voltage [V]
DS
Figure 5. Capacitance Characteristics
102
101
http://www.DataSheet4U.net/
100
0.2
17525
Notes :
1.
2.
2V5GS0μ=s0VPulse
Test
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD, Source-Drain voltage [V]
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
V = 15V
10 DS
V = 24V
DS
8
6
4
2
Note : ID = 60A
0
0 5 10 15 20 25 30 35
Q , Total Gate Charge [nC]
G
Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
datasheet pdf - http://www.DataSheet4U.net/

3 Page

P60N03L pdf
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
Same Type
as DUT
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
Gate Pulse Widthhttp://www.DataSheet4U.net/
D = --------------------------
Gate Pulse Period
10V
IFM , Body Diode Forward Current
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
Body Diode
Forward Voltage Drop
VDD
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
datasheet pdf - http://www.DataSheet4U.net/

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