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PDF DS3065WP Fiche technique - Maxim Integrated Products

Numéro de référence DS3065WP
Description Nonvolatile SRAM
Fabricant Maxim Integrated Products 
Logo Maxim Integrated Products Logo 



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DS3065WP Datasheet, Description
DataSheet.in
19-5450; Rev 0; 7/10
3.3V, 8Mb, Nonvolatile SRAM with Clock
General Description
The DS3065WP consists of a static RAM, a nonvolatile
(NV) controller, and a real-time clock (RTC). These com-
ponents are packaged on a surface-mount substrate
and require post-assembly attachment of a DS9034I-
PCX+ battery cap. Whenever VCC is applied to the
module, it powers the clock and SRAM from the external
power source, and allows the contents of the clock reg-
isters or SRAM to be modified. When VCC is powered
down or out of tolerance, the controller write protects the
memory contents and powers the clock and SRAM from
the battery.
Features
S Reflowable, 34-Pin PowerCap Package
S Integrated RTC
S Unconditionally Write Protects the Clock and
SRAM When VCC is Out of Tolerance
S Automatically Switches to Battery Supply When
VCC Power Failures Occur
S Extended Industrial Temperature Range (-40NC to
+85NC)
S Underwriters Laboratories Recognized
Applications
RAID Systems and Servers/Gaming
POS Terminals/Fire Alarms
Industrial Controllers/PLCs
Data-Acquisition Systems
Routers/Switches
PART
DS3065WP-100IND+
TEMP RANGE
-40NC to +85NC
SPEED (ns)
100
Ordering Information
SUPPLY VOLTAGE (V)
3.3 Q0.3
PIN-PACKAGE
34 PowerCap Module
Typical Operating Circuit
CE
WR
RD
CS
MICROPROCESSOR
OR DSP
DATA
ADDRESS
8 BITS
20 BITS
CE
WE
OE
CS
DS3065WP
1024k x 8
NV SRAM
AND RTC
DQ0–DQ7
A0–A19
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
DS3065WP Fiche technique
DataSheet.in
3.3V, 8Mb, Nonvolatile SRAM with Clock
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.3V Q0.3V, TA = -40NC to +85NC, unless otherwise noted.)
PARAMETER
Output High Impedance from
Deselection
Output Hold from Address
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Impedance from WE
Output Active from WE
Data Setup Time
Data Hold Time
Chip-to-Chip Setup Time
SYMBOL
tOD (Note 2)
tOH
tWC
tWP
tAW
tWR1
tWR2
tODW
tOEW
tDS
tDH1
tDH2
tCCS
(Note 3)
(Note 4)
(Note 5)
(Note 2)
(Note 2)
(Note 6)
(Note 4)
(Note 5)
CONDITIONS
POWER-DOWN/POWER-UP TIMING
(TA = -40NC to +85NC, unless otherwise noted.)
PARAMETER
SYMBOL
VCC Fail Detect to CE, CS, and
WE Inactive Time
VCC Slew from VTP to 0V
VCC Slew from 0V to VTP
VCC Valid to CE, CS, and WE
Inactive
tPD (Note 7)
tF
tR
tPU
VCC Valid to End of Write
Protection
tREC
CONDITIONS
DATA RETENTION
(TA = +25NC, unless otherwise noted.)
PARAMETER
Expected Data-Retention Time
SYMBOL
tDR
(Notes 7, 8)
CONDITIONS
AC TEST CONDITIONS
Voltage Range on Any Pin Relative to Ground: -0.3V to +4.6V
Input Pulse Levels: VIL = 0V, VIH = 2.7V
Input Pulse Rise and Fall Times: 5ns
Input and Output Timing Reference Level: 1.5V
Output Load: 1 TTL Gate + CL (100pF) including scope and jig
MIN TYP MAX UNITS
40 ns
5 ns
100 ns
75 ns
0 ns
5
20
ns
40 ns
5 ns
40 ns
0
20
ns
40 ns
MIN TYP MAX UNITS
1.5 Fs
150 Fs
150 Fs
2 ms
125 ms
MIN TYP MAX UNITS
10 Years
3

3 Page

DS3065WP pdf
DataSheet.in
3.3V, 8Mb, Nonvolatile SRAM with Clock
Note 1: All voltages are referenced to ground.
Note 2: These parameters are sampled with a 5pF load and are not 100% tested.
Note 3: tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWP is measured from
the later of the two related edges going low to the earlier of the two related edges going high.
Note 4: tWR1 and tDH1 are measured from WE going high.
Note 5: tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes.
Note 6: tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for
RTC writes.
Note 7: In a power-down condition, the voltage on any pin cannot exceed the voltage on VCC.
Note 8: The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied
by the user. Minimum expected data-retention time is based upon a single convection reflow exposure, followed by an
attachment of a new DS9034I-PCX+. This parameter is assured by component selection, process control, and design. It
is not measured directly during production testing.
Note 9: WE is high for any read cycle.
Note 10: VOE = VIH or VIL. If VOE = VIH during write cycle, the output buffers remain in a high-impedance state.
Note 11: If the CE or CS low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a
high-impedance state during this period.
Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a
high-impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output
buffers remain in a high-impedance state during this period.
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