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PDF DS31400 Fiche technique - Maxim Integrated Products

Numéro de référence DS31400
Description Dual DPLL Timing IC
Fabricant Maxim Integrated Products 
Logo Maxim Integrated Products Logo 



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DS31400 Datasheet, Description
19-5256; Rev 0; 4/10
ABRIDGED DATA SHEET
www.DataSheet4U.com
DS31400
8-Input, 14-Output, Dual DPLL Timing IC
with Sub-ps Output Jitter
General Description
Features
The DS31400 is a flexible, high-performance timing IC
for diverse frequency conversion and frequency
synthesis applications. On each of its eight input clocks
and 14 output clocks, the device can accept or generate
nearly any frequency between 2kHz and 750MHz. The
device offers two independent DPLLs to serve two
independent clock-generation paths.
The input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for
each of the two flexible, high-performance digital PLLs.
Each DPLL lock to the selected reference and provides
programmable bandwidth, very high-resolution holdover
capability and truly hitless switching between input
clocks. The digital PLLs are followed by a clock
synthesis subsystem, which has seven fully
programmable digital frequency synthesis blocks, three
high-speed low-jitter APLLs, and 14 output clocks, each
with its own 32-bit divider and phase adjustment. The
APLLs provide fractional scaling and output jitter less
than 1ps RMS.
For telecom systems, the device has all required
features and functions to serve as a central timing
function or as a line card timing IC. With a suitable
oscillator the DS31400 meets the requirements of
Stratum 2, 3E, 3, 4E and 4; G.812 Types I–IV; G.813;
and G.8262.
Applications
Frequency Conversion Applications in a Wide Variety of
Equipment Types
Telecom Line Cards or Timing Cards with Any Mix of
SONET/SDH, Synchronous Ethernet, and/or OTN Ports
in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
DS31400GN
-40C to +85C 256 CSBGA
DS31400GN+ -40C to +85C 256 CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
Eight Input Clocks
Differential or CMOS/TTL Format
Any Frequency from 2kHz to 750MHz
Fractional Scaling for 64B/66B and FEC Scaling (e.g.,
64/66, 237/255, 238/255) or Any Other
Downscaling Requirement
Continuous Input Clock Quality Monitoring
Automatic or Manual Clock Selection
Three 2/4/8kHz Frame Sync Inputs
Two High-Performance DPLLs
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Holdover on Loss of All Inputs
Programmable Bandwidth, 0.5mHz to 400Hz
Seven Digital Frequency Synthesizers
Each Can Slave to Either DPLL
Produce Any 2kHz Multiple Up to 77.76MHz
Per-DFS Clock Phase Adjust
Three Output APLLs
Output Frequencies to 750MHz
High Resolution Fractional Scaling for FEC and
64B/66B (e.g., 255/237, 255/238, 66/64) or Any
Other Scaling Requirement
Less than 1ps RMS Output Jitter
Simultaneously Produce Three Low-Jitter Rates from
the Same Reference (e.g., 622.08MHz for
SONET, 255/237 x 622.08MHz for OTU2, and
156.25MHz for 10GE)
14 Output Clocks in Seven Groups
Nearly Any Frequency from < 1Hz to 750MHz
Each Group Slaves to a DFS Clock, Any APLL Clock,
or Any Input Clock (Divided and Scaled)
Each Has a Differential Output (Three CML, Four LVDS/
LVPECL) and Separate CMOS/TTL Output
32-Bit Frequency Divider per Output
Two Sync Pulse Outputs: 8kHz and 2kHz
General Features
Suitable Line Card IC or Timing Card IC for Stratum
2/3E/3/4E/4, SMC, SEC/EEC, or SSU
Accepts and Produces Nearly Any Frequency Up to
750MHz, Including 1Hz, 2kHz, 8kHz, NxDS1,
NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,
156.25M, and Nx19.44M Up to 622.08M
Internal Compensation for Local Oscillator Frequency
Error
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
DS31400 Fiche technique
ABRIDGED DATA SHEET
Block Diagram
www.DDatSaS3he1et44U0.c0om
SYNC1
SYNC2
SYNC3
DS31400
IC1 POS/NEG
IC2 POS/NEG
IC3 POS/NEG
IC4 POS/NEG
IC5 POS/NEG
IC6 POS/NEG
IC7 POS/NEG
IC8 POS/NEG
Input Clock
Block
Frequency Scaler,
Activity Monitor,
Freq. Monitor,
Optional Inversion
(per input clock)
8
status
JTRST
JTMS
JTCLK
JTDI
JTDO
JTAG
PLL Bypass
DPLL1
Filtering, Holdover,
Hitless Switching, PBO,
Frequency Conversion,
Manual Phase Adjust
DPLL2
identical to DPLL1
Clock
Selector
MFSYNC
DFS Muxes
DFS 1
DFS 2
DFS 3
APLL1
APLL2
APLL3
DFS 4
DFS 5
DFS 6
DFS 7
FSYNC
MFSYNC
Divider Muxes
Dif Muxes
Divider 1
lowest jitter path
OC1
OC1POS/NEG
Divider 2
lowest jitter path
OC2
OC2POS/NEG
Divider 3
lowest jitter path
OC3
OC3POS/NEG
Divider 4
OC4
OC4POS/NEG
Divider 5
OC5
OC5POS/NEG
Divider 6
OC6
OC6POS/NEG
Divider 7
OC7
OC7POS/NEG
Microprocessor Port
(SPI Serial)
and HW Control and Status Pins
Master Clock
APLL
MCLKOSC
Local Oscillator
TCXO or OCXO
________________________________________________________ Maxim Integrated Products 3

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