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PDF DS3171 Fiche technique - Maxim

Numéro de référence DS3171
Description Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
Fabricant Maxim 
Logo Maxim Logo 



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DS3171 Datasheet, Description
www.maxim-ic.com
www.DataSheet4U.com
DS3171/DS3172/DS3173/DS3174
Single/Dual/Triple/Quad
DS3/E3 Single-Chip Transceivers
GENERAL DESCRIPTION
The DS3171, DS3172, DS3173, and DS3174
(DS317x) combine a DS3/E3 framer(s) and LIU(s) to
interface to as many as four DS3/E3 physical copper
lines.
APPLICATIONS
Access Concentrators
SONET/SDH ADM
and Muxes
PBXs
Digital Cross Connect
Test Equipment
Routers and Switches
Multiservice Access
Platform (MSAP)
Multiservice Protocol
Platform (MSPP)
PDH Multiplexer/
Demultiplexer
Integrated Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3171*
DS3171N*
DS3172*
DS3172N*
DS3173*
DS3173N*
DS3174
DS3174N
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
*Future product—contact factory for availability.
FUNCTIONAL DIAGRAM
DS3/E3
PORTS
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
DS317x
FEATURES
§ Single (DS3171), Dual (DS3172), Triple
(DS3173), or Quad (DS3174) Single-Chip
Transceiver for DS3 and E3
§ All Four Devices are Pin Compatible for Ease of
Port Density Migration in the Same Printed
Circuit Board Platform
§ Each Port Independently Configurable
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 meters, or 1246 feet (DS3) or 440 meters, or
1443 feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
§ Ports Independently Configurable for DS3, E3
§ Built-In HDLC Controllers with 256-Byte FIFOs
for the Insertion/Extraction of DS3 PMDL, G.751
Sn Bit, and G.832 NR/GC Bytes
§ On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second
§ Flexible Overhead Insertion/Extraction Ports for
DS3, E3 Framers
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102204
DS3171 Fiche technique
DS3171/DS3172/DS3173/DS3174
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1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at each LIU interface for proper operation. Figure 1-2 shows
the functional block diagram of one channel DS3/E3 LIU.
Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device
Transmit
Receive
1:2ct
1:2ct
Each DS3/E3 LIU Interface
TXP
330W
(1%)
TXN
VDD
VDD
VDD
0.01uF 0.1uF 1uF
0.01uF 0.1uF 1uF
0.01uF 0.1uF 1uF
3.3V
Power
Plane
RXP
330W
(1%)
RXN
VSS
VSS
VSS
Ground
Plane
Figure 1-2. DS317x Functional Block Diagram
TPOSn/TDATn
TNEGn
TLCLKn
TXPn
TXNn
DS3/E3
Transmit
LIU
RDATn
RNEGn/ RLCVn
RLCLKn
RXPn
RXNn
DS3/E3
Receive
LIU
Clock Rate
Adapter
TAIS
TUA1
B3ZS/
HDB3
Encoder
DS3 / E3
Transmit
Formatter
Trail
FEAC Trace HDLC
Buffer
DS317x
TX BERT
RX BERT
B3ZS/
HDB3
Decoder
Microprocessor
Interface
DS3 / E3
Receive
Framer
UA1
GEN
IEEE P1149.1
JTAG Test
Access Port
TCLKIn
TSERn
TSOFIn
RSERn
RCLKOn/RGCLKn
RSOFOn/RDENn
n = port # (1-4)
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DS3171 pdf
DS3171/DS3172/DS3173/DS3174
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10.10.4 Transmit Line Interface ...................................................................................................................... 105
10.10.5 Receive Line Interface ....................................................................................................................... 105
10.10.6 B3ZS/HDB3 Decoder ......................................................................................................................... 105
10.11 BERT......................................................................................................................................................... 107
10.11.1 General Description ........................................................................................................................... 107
10.11.2 Features ............................................................................................................................................. 107
10.11.3 Configuration and Monitoring ............................................................................................................. 107
10.11.4 Receive Pattern Detection ................................................................................................................. 108
10.11.5 Transmit Pattern Generation.............................................................................................................. 110
10.12 LIU – LINE INTERFACE UNIT ........................................................................................................................ 111
10.12.1 General Description ........................................................................................................................... 111
10.12.2 Features ............................................................................................................................................. 111
10.12.3 Detailed Description ........................................................................................................................... 112
10.12.4 Transmitter ......................................................................................................................................... 112
10.12.5 Receiver ............................................................................................................................................. 113
11 OVERALL REGISTER MAP
116
12 REGISTER MAPS AND DESCRIPTIONS
119
12.1 REGISTERS BIT MAPS.................................................................................................................................. 119
12.1.1 Global Register Bit Map ..................................................................................................................... 119
12.1.2 HDLC Register Bit Map...................................................................................................................... 122
12.1.3 T3 Register Bit Map ........................................................................................................................... 124
12.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
12.1.6 Clear Channel Register Bit Map ........................................................................................................ 126
12.2 GLOBAL REGISTERS .................................................................................................................................... 127
12.2.1 Register Bit Descriptions.................................................................................................................... 127
12.3 PER PORT COMMON.................................................................................................................................... 135
12.3.1 Register Bit Descriptions.................................................................................................................... 135
12.4 BERT......................................................................................................................................................... 146
12.4.1 BERT Register Map ........................................................................................................................... 146
12.4.2 BERT Register Bit Descriptions ......................................................................................................... 146
12.5 B3ZS/HDB3 LINE ENCODER/DECODER ....................................................................................................... 153
12.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 153
12.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 154
12.6 HDLC......................................................................................................................................................... 158
12.6.1 HDLC Transmit Side Register Map.................................................................................................... 158
12.6.2 HDLC Receive Side Register Map..................................................................................................... 161
12.7 FEAC CONTROLLER ................................................................................................................................... 165
12.7.1 FEAC Transmit Side Register Map.................................................................................................... 165
12.7.2 FEAC Receive Side Register Map..................................................................................................... 167
12.8 TRAIL TRACE............................................................................................................................................... 170
12.8.1 Trail Trace Transmit Side................................................................................................................... 170
12.8.2 Trail Trace Receive Side Register Map ............................................................................................. 171
12.9 DS3/E3 FRAMER ........................................................................................................................................ 176
12.9.1 Transmit DS3 ..................................................................................................................................... 176
12.9.2 Receive DS3 Register Map................................................................................................................ 178
12.9.3 Transmit G.751 E3 ............................................................................................................................. 186
12.9.4 Receive G.751 E3 Register Map ....................................................................................................... 188
12.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 193
12.9.6 Receive G.832 E3 Register Map ....................................................................................................... 196
12.9.7 Transmit Clear Channel ..................................................................................................................... 204
12.9.8 Receive Clear Channel ...................................................................................................................... 205
13 JTAG INFORMATION
207
13.1 JTAG DESCRIPTION.................................................................................................................................... 207
13.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................. 207
13.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................................... 209
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