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PDF DS3154 Fiche technique - Dallas

Numéro de référence DS3154
Description Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Fabricant Dallas 
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DS3154 Datasheet, Description
DEMO KIT AVAILABLE
www.maxim-ic.com
DS3151/DS3152/DS3153/DS3154
Single/Dual/Triple/Quad
DS3/E3/STS-1 LIUs
GENERAL DESCRIPTION
The DS3151 (single), DS3152 (dual), DS3153
(triple), and DS3154 (quad) line interface units (LIUs)
perform the functions necessary for interfacing at the
physical layer to DS3, E3, or STS-1 lines. Each LIU
has independent receive and transmit paths and a
built-in jitter attenuator.
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
FUNCTIONAL DIAGRAM
LINE IN
DS3, E3,
OR STS-1
EACH LIU
RXP
RXN
CLK
DATA
Dallas
Semiconductor
DS315x
LINE OUT
DS3, E3,
OR STS-1
TXP
TXN
CLK
DATA
RECEIVE
CLOCK
AND DATA
CONTROL
STATUS
TRANSMIT
CLOCK
AND DATA
FEATURES
Single, Dual, Triple, or Quad Integrated
Transmitter, Receiver, and Jitter Attenuators for
DS3, E3, and STS-1
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
Hardware or CPU Bus Configuration Options
Jitter Attenuators can be Placed in Either the
Receive or Transmit Paths
Interface to 75Ω Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Use 1:2 Transformers on Tx and Rx
Require Minimal External Components
Local and Remote Loopbacks
Low-Power 3.3V Operation (5V Tolerant I/O)
Industrial Temperature Range: -40°C to +85°C
Small Package: 144-Pin, 13mm x 13mm
Thermally Enhanced CSBGA
IEEE 1149.1 JTAG Support
Features continued on page 5.
ORDERING INFORMATION
PART
DS3151
DS3151N
DS3152
DS3152N
DS3153
DS3153N
DS3154
DS3154N
LIUs
1
1
2
2
3
3
4
4
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 030607
DS3154 Fiche technique
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
LIST OF FIGURES
Figure 1-1. External Connections ...............................................................................................................7
Figure 2-1. 4-Port Unchannelized DS3/E3 Card.........................................................................................7
Figure 3-1. Hardware Mode Block Diagram ...............................................................................................8
Figure 3-2. CPU Bus Mode Block Diagram ................................................................................................9
Figure 5-1. Status Register Logic .............................................................................................................16
Figure 6-1. Receiver Jitter Tolerance .......................................................................................................24
Figure 7-1. E3 Waveform Template .........................................................................................................27
Figure 7-2. DS3 AIS Structure ..................................................................................................................28
Figure 8-1. PRBS Output with Normal RCLK Operation ..........................................................................29
Figure 8-2. PRBS Output with Inverted RCLK Operation .........................................................................29
Figure 9-1. Jitter Attenuation/Jitter Transfer .............................................................................................30
Figure 12-1. JTAG Block Diagram............................................................................................................32
Figure 12-2. JTAG TAP Controller State Machine....................................................................................33
Figure 13-1. Transmitter Framer Interface Timing Diagram .....................................................................38
Figure 13-2. Receiver Framer Interface Timing Diagram .........................................................................39
Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) ........................................................................41
Figure 13-4. CPU Bus Timing Diagram (Multiplexed)...............................................................................43
Figure 13-5. JTAG Timing Diagram..........................................................................................................45
Figure 14-1. DS3151 Hardware Mode Pin Assignment............................................................................51
Figure 14-2. DS3151 CPU Bus Mode Pin Assignment.............................................................................52
Figure 14-3. DS3152 Hardware Mode Pin Assignment............................................................................53
Figure 14-4. DS3152 CPU Bus Mode Pin Assignment.............................................................................54
Figure 14-5. DS3153 Hardware Mode Pin Assignment............................................................................55
Figure 14-6. DS3153 CPU Bus Mode Pin Assignment.............................................................................56
Figure 14-7. DS3154 Hardware Mode Pin Assignment............................................................................57
Figure 14-8. DS3154 CPU Bus Mode Pin Assignment.............................................................................58
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3 Page

DS3154 pdf
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 1-A. Applicable Telecommunications Standards
SPECIFICATION
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
G.703
G.751
G.775
G.823
G.824
O.151
ETS 300 686
ETS 300 687
ETS EN 300 689
TBR 24
GR-253-CORE
GR-499-CORE
SPECIFICATION TITLE
ANSI
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Formats Specification
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
ITU-T
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the
Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November 1994
The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps
Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October 1992
ETSI
Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,
D34S, D140U, and D140S); Network Interface Presentation, 1996
Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);
Connection Characteristics, 1996
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;
Attachment Requirements for Terminal Equipment Interface, 1997
TELCORDIA
SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1,
December 1998
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