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PDF ADN8830 Fiche technique ( Data sheet )

Numéro de référence ADN8830
Description Thermoelectric Cooler Controller
Fabricant Analog Devices 
Logo Analog Devices Logo 



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ADN8830 Datasheet, Description
FEATURES
High Efficiency
Small Size: 5 mm ؋ 5 mm LFCSP
Low Noise: <0.5% TEC Current Ripple
Long-Term Temperature Stability: ؎0.01؇C
Temperature Lock Indication
Temperature Monitoring Output
Oscillator Synchronization with an External Signal
Clock Phase Adjustment for Multiple Controllers
Programmable Switching Frequency up to 1 MHz
Thermistor Failure Alarm
Maximum TEC Voltage Programmability
APPLICATIONS
Thermoelectric Cooler (TEC) Temperature Control
Resistive Heating Element Control
Temperature Stabilization Substrate (TSS) Control
Thermoelectric Cooler Controller
ADN8830
GENERAL DESCRIPTION
The ADN8830 is a monolithic controller that drives a thermo-
electric cooler (TEC) to stabilize the temperature of a laser diode
or a passive component used in telecommunications equipment.
This device relies on a negative temperature coefficient (NTC)
thermistor to sense the temperature of the object attached to the
TEC. The target temperature is set with an analog input voltage
either from a DAC or an external resistor divider.
The loop is stabilized by a PID compensation amplifier with
high stability and low noise. The compensation network can be
adjusted by the user to optimize temperature settling time. The
component values for this network can be calculated based on
the thermal transfer function of the laser diode or obtained
from the lookup table given in the Application Notes section.
Voltage outputs are provided to monitor both the temperature of
the object and the voltage across the TEC. A voltage reference
of 2.5 V is also provided.
FROM
THERMISTOR
TEMPERATURE
SET
INPUT
VREF
FUNCTIONAL BLOCK DIAGRAM
PID COMPENSATION
NETWORK
TEMPERATURE
MEASUREMENT
AMPLIFIER
PWM
CONTROLLER
VOLTAGE
REFERENCE
OSCILLATOR
MOSFET
DRIVERS
P-CHANNEL
(UPPER MOSFET)
N-CHANNEL
P-CHANNEL
(LOWER MOSFET)
N-CHANNEL
FREQUENCY/PHASE
CONTROL
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113 © 2012 Analog Devices, Inc. All rights reserved.
ADN8830 Fiche technique
ADN8830–SPECIFICATIONS (@ VDD = 3.3 V to 5.0 V, VGND = 0 V, TA = 25؇C, TSET = 25؇C, using typical application
configuration as shown in Figure 1, unless otherwise noted.)
Parameter
Symbol Conditions
TEMPERATURE STABILITY
Long-Term Stability
Using 10 kΩ thermistor with
= –4.4% at 25°C
PWM OUTPUT DRIVERS
Output Transition Time
Nonoverlapping Clock Delay
Output Resistance
Output Voltage Swing
Output Voltage Ripple
Output Current Ripple
LINEAR OUTPUT AMPLIFIER
Output Resistance
Output Voltage Swing
tR, tF
CL = 3,300 pF
RO (N1, P1)
OUT A
OUT A
ITEC
IL = 50 mA
VLIM = 0 V
fCLK = 1 MHz
fCLK = 1 MHz
RO, P2
RO, N2
OUT B
IOUT = 2 mA
IOUT = 2 mA
POWER SUPPLY
Power Supply Voltage
Power Supply Rejection Ratio
VDD
PSRR
Supply Current
ISY
Shutdown Current
Soft-Start Charging Current
Undervoltage Lockout
ERROR AMPLIFIER
Input Offset Voltage
Gain
Input Voltage Range
Common-Mode Rejection Ratio
ISD
ISS
VOLOCK
VOS
AV, IN
VCM
CMRR
Open-Loop Input Impedance
Gain-Bandwidth Product
RIN
GBW
VDD = 3.3 V to 5 V, VTEC = 0 V
–40°C TA +85°C
PWM not switching
–40°C TA +85°C
Pin 10 = 0 V
Low-to-high threshold
VCM = 1.5 V
0.2 V < VCM < 2.0 V
–40°C TA +85°C
REFERENCE VOLTAGE
Reference Voltage
OSCILLATOR
Synchronization Range
Oscillator Frequency
VREF
fCLK
fCLK
IREF < 2 mA
Pin 25 connected to external clock
Pin 24 = VDD; (R = 150 kΩ;
Pin 25 = GND)
LOGIC CONTROL*
Logic Low Input Threshold
Logic High Input Threshold
Logic Low Output Level
Logic High Output Threshold
*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA).
Specifications subject to change without notice.
Min Typ
20
50 65
6
0
0.2
0.2
85
178
0
3.0
80 92
60
8
5
15
2.0
50
20
0.2
58 68
55
1
2
2.37 2.47
200
800 1,000
3
VDD – 0.2
Max Unit
0.01 °C
ns
ns
Ω
VDD
V
%
%
Ω
Ω
VDD
V
5.5 V
dB
dB
12 mA
15 mA
μA
μA
2.7 V
250 μV
V/V
2.0 V
dB
dB
GΩ
MHz
2.57 V
1,000 kHz
1,250 kHz
0.2 V
V
0.2 V
V
–2– REV. D

3 Page

ADN8830 pdf
Typical Performance Characteristics–ADN8830
VDD = 5V
TA = 25؇C
P1
N1
0
000000 0000
TIME (20ns/DIV)
TPC 1. N1 and P1 Rise Time
0
360
SYNC IN = 200kHz
320 TA = 25؇C
280
240
200
160
120
80
40
0
0 0.4 0.8 1.2 1.6 2.0 2.4
VPHASE (V)
TPC 4. Clock Phase Shift vs. Phase Voltage
VDD = 5V
TA = 25؇C
P1
N1
0
000000 0000
TIME (20ns/DIV)
TPC 2. N1 and P1 Fall Time
0
2.480
2.475
2.470
2.465
2.460
2.455
–40
–15 10 35 60
TEMPERATURE (؇C)
TPC 5. VREF vs. Temperature
85
360
SYNC IN = 1MHz
320 TA = 25؇C
280
240
200
160
120
80
40
0
0 0.4 0.8 1.2 1.6 2.0 2.4
VPHASE (V)
TPC 3. Clock Phase Shift vs. Phase Voltage
1,000
800
VDD = 5V
TA = 25؇C
600
400
200
0
0 250 500 750 1,000 1,250 1,500
RFREQ (k)
TPC 6. Switching Frequency vs. RFREQ
REV. D
–5–

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