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PDF H6060 Fiche technique - EM Microelectronic - MARIN SA

Numéro de référence H6060
Description Self Recovering Watchdog
Fabricant EM Microelectronic - MARIN SA 
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H6060 Datasheet, Description
EM MICROELECTRONIC - MARIN SA
DATASHEET Ɩ H6060
Self Recovering Watchdog
Description
The H6060 is a monolithic low-power CMOS device
combining a programmable timer and a series of voltage
comparators on the same chip. The device is specially
suited for watchdog functions such as microprocessor and
supply voltage monitoring. If the P system malfunctions,
the watchdog will recover it by issuing repeated active reset
signals. The voltage monitoring part provides double
security by combining both the unregulated voltage (VIN)
and the regulated voltage (VDD) monitoring simultaneously.
The H6060 initializes the power-on reset after VIN reaches
VSH (see table 4) and VDD rises above 3.V. If VIN drops
below VSL (see table 4), the H6060 gives an advanced
warning signal for register saving and if the voltage drops
further below VRL (see table 4), RES and RES go active.
The H6060 functions at any supply voltage down to 1.6 V
and is therefore particularly suited for start-up and shut-
down control of microprocessor systems.
Typical Operating Configuration
Features
Self recovering watchdog function: reset goes active
after the 1st timeout period, reset goes inactive again
after the 2nd timeout period, repeated active reset signal
until the system recovers
Standard timeout period and power-on reset time (100
ms), externally programmable if required
Unregulated DC monitoring (VIN) with 3 standard or
programmable trigger voltages for: power-on reset
initialization, advanced power-fail warning ( SAVE ),
reset at power-down ( RES )
Regulated DC monitoring (VDD): power-on reset
initialization enabled only if VDD 3.5 V
Internal voltage reference
Works down to 1.6 V supply voltage
Push-pull or Open drain outputs
Low current consumption
SO8 package
Applications
Microprocessor and microcontroller systems
Point of sales equipment
Telecom products
Automotive subsystems
Pin Assignment
Voltage
Regulator
5V
VIN
TCL
VSS
VDD
RES
SAVE
RES
NMI
RES
I/O
Micro-
processor
GND
SO8
VIN
TCL
RC
VSS
H6060
VDD
RES
SAVE
RES
Fig. 1
Fig. 2
Copyright 2016, EM Microelectronic-Marin SA
6060-DS, Version 2.0, 3-Aug-16
1
www.emmicroelectronic.com
420005-A01, 3.0
H6060 Fiche technique
Timing Characteristics
VDD = 5.0 V, TA = 40 C to 85 C, unless otherwise specified
Parameter
Symbol
Test Conditions
Propagation delays
TCL to output pins
VIN to output pins
Logic transition times on
all output pins
Timeout period
TTCL input pulse width
Power-on reset debounce
VIN low pulse
TDIDO
TAIDO
TTR
TTO
TTO
TTCL
TDB
TVINL
Excluding debounce time TDB
Load 10 k, 100 pF
RC open, unshielded, TA = 25 C
RC open, unshielded (not tested)
Where debounce time TDB
Is guaranteed
Timing Waveforms
Voltage Reaction: VDD Monitoring
DATASHEET Ɩ H6060
Min. Typ. Max. Units
250 500
4 10
30 100
60 100 160
45 200
150
TTO/64
10
ns
s
ns
ms
ms
ns
ms
s
Table 5
VDD
VON
VOFF
VIN monitoring enabled
Voltage Reaction: VIN Monitoring
VIN
VSH
VSL
VRL
0
SAVE
RES
RES
TTO
TDB
TVIN
L
TTO
TDB
Timer
Start Power-on Reset
Timer
Stop Timer
Start
Power-on Reset No Power-on Reset
(as VIN VRL)
Fig. 3
Conditions:
VDD VON.
No timeout.
Fig. 4
Copyright 2016, EM Microelectronic-Marin SA
6060-DS, Version 2.0, 3-Aug-16
3
www.emmicroelectronic.com
420005-A01, 3.0

3 Page

H6060 pdf
DATASHEET Ɩ H6060
Timer Programming
With pin RC unconnected, the on-chip RC oscillator
together with its divider chain give a timeout TTO of typically
100 ms. To program different TTO, an approximation for
calculating component values is given by the formula:

TTO
0.75

(32 C1) 2
5.5
VDD 1
R1 
8.192
R1 min. = 10 k, C1 max. = 1 F
If R1 is in Mand C1 in pF, TTO will be in ms.
A resistor decreases and a capacitor increases the interval
to timeout. Excellent temperature stability of TTO can be
achieved by using external components. A precise square
wave of period 2 TTO is generated at the outputs RES
and RES when TCL is tied to either VDD or VSS. The
oscillator and watchdog timer start running when both VIN is
greater than VSH (see Fig. 6) and VDD is greater than VON
(see Fig. 3).
They will remain running while both VIN is greater than VRL
and VDD is greater than VOFF (see Fig. 3).
Timer Clearing and RES /RES Action
A negative edge or a negative pulse at the TCL input for
longer than 150 ns will reset the timer and set RES and
RES inactive. If a further TCL signal edge or pulse is
applied before TTO timeout, RES and RES will remain
inactive and the timer will again be reset to zero (see Fig.
5). If no TCL signal is applied before the TTO timeout, RES
and RES will start to generate square waves of period 2
TTO starting with the inactive state. The watchdog will
remain in this state until the next TCL signal appears, or
until a fresh power-up sequence.
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated
by the sequence of events shown in Fig. 6. One timeout
period after VIN reaches VSH, during power-up, RES and
RES go inactive. A TCL pulse will have no effect until this
power-on reset delay is completed. After completing the
power-up sequence the watchdog timer starts acting. If no
TCL pulse occurs, RES and RES go active after one
timeout period TTO. After each subsequent timeout period,
without a timer clear pulse at TCL , RES and RES change
polarity providing square wave signals. A TCL pulse clears
the watchdog timer and causes RES and RES to go
inactive. A voltage drop below the VRL level overrides the
timer and immediately forces RES , RES and SAVE
active. Any further TCL pulse has no effect until the next
power-up sequence is completed.
Typical Applications
Microprocessor Watchdog with Power-On Reset and Voltage Monitor
Unregulated
Voltage
R1 = 470 k
Address SEL
Decoder
Latched
Address Bus
C1 =
220 pF
Voltage
Regulator
5 V Regulated
Voltage
VIN
TCL
RC
VSS
VDD
RES
SAVE
RES
RD
Microprocessor
RESET
IRQ
RAM
CS
CS
Fig. 10
Copyright 2016, EM Microelectronic-Marin SA
6060-DS, Version 2.0, 3-Aug-16
6
www.emmicroelectronic.com
420005-A01, 3.0

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