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PDF 74HC573D Fiche technique - Toshiba

Numéro de référence 74HC573D
Description CMOS Digital Integrated Circuits
Fabricant Toshiba 
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74HC573D Datasheet, Description
CMOS Digital Integrated Circuits Silicon Monolithic
74HC573D
74HC573D
1. Functional Description
• Octal D-Type Latch with 3-State Outputs
2. General
The 74HC573D is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
These 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).
When the OE input is high, the eight outputs are in a high impedance state.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1) High speed: tpd = 13 ns (typ.) at VCC = 6.0 V
(2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25
(3) Balanced propagation delays: tPLH tPHL
(4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V
4. Packaging
SOIC20
©2016 Toshiba Corporation
1
Start of commercial production
2016-03
2016-05-24
Rev.2.0
74HC573D Fiche technique
8. Truth Table
INPUT
OE
INPUT
LE
INPUT
D
OUTPUT
Q
HXXZ
L L X Qn
LHL L
L HHH
X: Don't Care
Z: High Impedance
Qn: Q outputs are latched at the time when
the LE input is taken to low logic level.
9. System Diagram
74HC573D
©2016 Toshiba Corporation
3
2016-05-24
Rev.2.0

3 Page

74HC573D pdf
74HC573D
12.3. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns)
Characteristics
Minimum pulse width
(LE)
Minimum setup time
Minimum hold time
Symbol
tw(H)
tS
th
Test Condition
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Limit
75
15
13
50
10
9
5
5
5
Unit
ns
ns
ns
12.4. Timing Requirements
(Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 6 ns)
Characteristics
Minimum pulse width
(LE)
Minimum setup time
Minimum hold time
Symbol
tw(H)
tS
th
Test Condition
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Limit
95
19
16
65
13
11
5
5
5
Unit
ns
ns
ns
©2016 Toshiba Corporation
6
2016-05-24
Rev.2.0

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