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PDF 74LVC125A Fiche technique - STMicroelectronics

Numéro de référence 74LVC125A
Description LOW VOLTAGE CMOS QUAD BUS BUFFERS
Fabricant STMicroelectronics 
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74LVC125A Datasheet, Description
74LVC125A
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 4.8ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC125A is a low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
applications.
SOP
TSSO P
ORDER CODES
PACKAGE
TUBE
SOP
TSSOP
74LVC125AM
T&R
74LVC125AMTR
74LVC125ATTR
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
These devices require the same 3-STATE control
input G to be taken high to make the output go in
to the high impedance state.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2002
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74LVC125A Fiche technique
74LVC125A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage (note 1)
VI Input Voltage
VO Output Voltage (High Impedance or VCC = 0V)
VO Output Voltage (High or Low State)
IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V)
IOH, IOL High or Low Level Output Current (VCC = 2.7 to 3.0V)
IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V)
IOH, IOL High or Low Level Output Current (VCC = 1.65 to 2.3V)
Top Operating Temperature
dt/dv Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
DC SPECIFICATIONS
Value
1.65 to 3.6
0 to 5.5
0 to 5.5
0 to VCC
± 24
± 12
±8
±4
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
mA
mA
°C
ns/V
Test Condition
Value
Symbol
VIH
VIL
VOH
VOL
II
Ioff
IOZ
ICC
ICC
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
ICC incr. per Input
VCC
(V)
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 3.6
1.65
2.3
2.7
3.0
3.0
1.65 to 3.6
1.65
2.3
2.7
3.0
3.6
0
3.6
3.6
2.7 to 3.6
IO=-100 µA
IO=-4 mA
IO=-8 mA
IO=-12 mA
IO=-18 mA
IO=-24 mA
IO=100 µA
IO=4 mA
IO=8 mA
IO=12 mA
IO=24 mA
VI = 0 to 5.5V
VI or VO = 5.5V
VI = VIH orVIL
VO = 0 to 5.5V
VI = VCC or GND
VI or VO = 3.6 to
5.5V
VIH = VCC-0.6V
-40 to 85 °C
-55 to 125 °C
Min. Max. Min. Max.
0.65VCC
0.65VCC
1.7 1.7
22
0.35VCC
0.35VCC
0.7 0.7
0.8 0.8
VCC-0.2
VCC-0.2
1.2 1.2
1.7 1.7
2.2 2.2
2.4 2.4
2.2 2.2
0.2 0.2
0.45 0.45
0.7 0.7
0.4 0.4
0.55 0.55
±5 ±5
10 10
±5 ±5
10
± 10
500
10
± 10
500
Unit
V
V
V
V
µA
µA
µA
µA
µA
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3 Page

74LVC125A pdf
74LVC125A
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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