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AOZ8804 Datasheet PDF - Alpha & Omega Semiconductors

Numéro de référence AOZ8804
Description Ultra-Low Capacitance TVS Diode Array
Fabricant Alpha & Omega Semiconductors 
Logo Alpha & Omega Semiconductors Logo 
avant-première
11 Pages
		
AOZ8804 Datasheet

1 Page

AOZ8804 Fiche technique
AOZ8804
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
Parameter
Conditions
Min. Typ. Max.
VRWM
VBR
IR
VF
VCL
Cj
Reverse Working Voltage
Reverse Breakdown Volt-
age
Reverse Leakage Current
Diode Forward Voltage
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Any I/O Pin to Ground
Channel Input Capacitance
Between I/O and VN(3)
IT = 1mA, between I/O and VN(4)
VRWM = 5V, between I/O and VN
IF = 15mA
IPP = 1A, tp = 100ns, any I/O pin to Ground(5)
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)
IPP = 1A, tp = 8/20µs
VR = 0V, f = 1MHz, between I/O pins
VR = 0V, f = 1MHz, any I/O pin to Ground
5.0
6.0
0.70 0.85
1
1
13.0
-3.0
18.0
-5.0
13.0
0.25 0.35
0.50 0.75
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Units
V
V
µA
V
V
V
V
V
V
pF
pF
Rev. 2.6 December 2010
www.aosmd.com
Page 3 of 11

3 Page

AOZ8804 pdf
AOZ8804
TDR for HDMI 1.3
The AOZ8804 TDR test results indicates the minimal
effect the low capacitance has on the HDMI 1.3 TDR
measurements. Below are the graphs from the TDR
measurements. The two graphs show the before and
after results of the TDR of each of the differential data
line (Clock, D0, D1, D2) of the HDMI when the AOZ8804
was populated onto the PCB, Figure 5 indicates the ideal
TDR of 100between the Cursor M1 and M2 where the
AOZ8804 would sit on top of the footprint.
125 125
120 120
115 115
110 110
105 105
100 100
95 95
90 90
85 85
80 80
75
-0.200 ns
(Step 2.56 ps)
0.100ns/
0.7500 ns
75
-0.200 ns
(Step 2.56 ps)
0.100ns/
0.7500 ns
Figure 3. Ideal Stripe-Line
Figure 4. With AOZ8804 Device on the Board
(TDR Measurement with 200pS Rise Time Using AOS Evaluation Board)
Figure 5 shows the graphical representation of the scope
photo of the TDR and the PCB board. The cursor M1
represent the edge of the connector in which the
M1 M2
equipment was calibrated to. The cursor M2 represent
the leveling off the the TDR when the signal passes
through the AOZ8804.
Number of Layers
Copper Trace Thickness
Dielectric Constant, εr
Overall Board Thickness
Dielectric Thickness Between
Top and Ground Layer
4
1.4 mils
4.6
62 mils
10 mils
AOZ8804
Figure 5. AOS HDMI Eval Board
Rev. 2.6 December 2010
www.aosmd.com
Page 6 of 11

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