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AOZ8804A Datasheet PDF - Alpha & Omega Semiconductors

Ultra-Low Capacitance TVS Diode

Numéro de référence AOZ8804A
Description Ultra-Low Capacitance TVS Diode
Fabricant Alpha & Omega Semiconductors 
Logo Alpha & Omega Semiconductors Logo 
avant-première
11 Pages
		
AOZ8804A Datasheet

1 Page

AOZ8804A Fiche technique
AOZ8804A
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
Parameter
VRWM
VBR
IR
VF
VCL
Cj
Reverse Working Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Diode Forward Voltage
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Any I/O Pin to Ground
Channel Input Capacitance
Conditions
Between I/O and VN(3)
IT = 1mA, between I/O and VN(4)
VRWM = 5V, between I/O and VN
IF = 15mA
IPP = 1A, tp = 100ns, any I/O pin to Ground(5)
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)
IPP = 12A, tp = 100ns, any I/O pin to Ground(5)
IPP = 1A, tp = 8/20µs
VR = 0V, f = 1MHz, between I/O pins
VR = 0V, f = 1MHz, any I/O pin to Ground
Min.
6.0
0.70
Typ.
0.85
Max.
5.0
1
1
12.0
-3.0
14.0
-5.0
16.5
-7.0
12.0
0.30 0.35
0.60 0.75
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Units
V
V
µA
V
V
V
V
V
V
V
V
pF
pF
Rev. 2.1 April 2015
www.aosmd.com
Page 3 of 11

3 Page

AOZ8804A pdf
AOZ8804A
High Speed PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8804A devices should be located as close as
possible to the noise source. The placement of the
AOZ8804A devices should be used on all data and
power lines that enter or exit the PCB at the I/O
connector. In most systems, surge pulses occur on data
and power lines that enter the PCB through the I/O
connector. Placing the AOZ8804A devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse can be coupled into
adjacent PCB traces. In addition, the PCB should use the
shortest possible traces. A short trace length equates to
low impedance, which ensures that the surge energy will
be dissipated by the AOZ8804A device. Long signal
traces will act as antennas to receive energy from fields
that are produced by the ESD pulse. By keeping line
lengths as short as possible, the efficiency of the line to
act as an antenna for ESD related fields is reduced.
Minimize interconnecting line lengths by placing devices
with the most interconnect as close together as possible.
The protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design.
The AOZ8804A ultra-low capacitance TVS is designed to
protect four high speed data transmission lines from
transient over-voltages by clamping them to a fixed
reference. The low inductance and construction
minimizes voltage overshoot during high current surges.
When the voltage on the protected line exceeds the
reference voltage the internal steering diodes are forward
biased, conducting the transient current away from the
sensitive circuitry. The AOZ8804A is designed for the
ease of PCB layout by allowing the traces to run
underneath the device. The pinout of the AOZ8804A is
designed to simply drop onto the IO lines of a High
Definition Multimedia Interface (HDMI) or USB 3.0 design
without having to divert the signal lines that may add
more parasitic inductance. Pins 1, 2, 4 and 5 are
connected to the internal TVS devices and pins 6, 7, 9
and 10 are no connects. The no connects was done so
the package can be securely soldered onto the PCB
surface.
Clock
Clock
Data0
Data0
Ground
Ground
Data1
Data1
Data2
Data2
Figure 6. Flow Through Layout for HDMI
SSRX+
SSRX+
SSRX–
SSRX–
Ground
Ground
SSTX+
SSTX+
SSTX–
SSTX–
Figure 7. Flow Through Layout for USB 3.0
Rev. 2.1 April 2015
www.aosmd.com
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