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PDF DSC400 Fiche technique - Micrel

Numéro de référence DSC400
Description Clock Generator
Fabricant Micrel 
Logo Micrel Logo 

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DSC400 Datasheet, Description
DSC400
Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
General Description
The DSC400 is a four output crystal-less™
clock generator. It utilizes Micrel’s proven
PureSiliconMEMS technology to provide
excellent jitter and stability while
incorporating additional device functionality.
The frequencies of the outputs can be
identical or independently derived from
common PLLs.
Each output may be configured
independently to support a single ended
LVCMOS interface or a differential interface.
Differential options include LVPECL, LVDS, or
HCSL.
The DSC400 provides two independent select
lines for choosing between two sets of pre-
configured frequencies per bank. It also has
two OE pins to allow for enabling and
disabling outputs.
The DSC400 is packaged in a 20-pin QFN
(5mm x 3.2mm) and is available in extended
commercial and industrial temperature
grades.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±25ppm, ±50ppm
Wide Temperature Range
o Ext. commercial: -20°C to 70°C
o Industrial: -40°C to 85°C
High Supply Noise Rejection: -50 dBc
Four format configurable outputs:
o LVPECL, LVDS, HCSL, LVCMOS
Available Pin-Selectable frequency table
o 1 pin per bank for 2 frequency sets
Wide Freq. Range:
o 2.3 MHz 460 MHz
20 QFN Footprint (5mm x 3.2mm)
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz based devices
Wide Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
AEC-Q100 Automotive Qualified
Block Diagram
Applications
Communications and Networks
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
HD/SD/SDI Video & Surveillance
Automotive
Media and Video
Embedded and Industrial
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DSC400
Page 1
DSC400 Fiche technique
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Operational Description
The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it
does not require an external crystal to operate; it relies on the integrated MEMS resonator that
interfaces with internal PLLs. This technology enhances performance and reliability by allowing
tighter frequency stability over a far wider temperature range. In addition, the higher resistance to
shock and vibration decreases the aging rate to allow for much improved product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection
to a high (1). Inputs can be controlled through hardware strapping method with a resistor to
ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs
In case more than one frequency set is desired, FSB1 and FSB2 are used for independently
selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)
and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.
If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to
disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
Table 1: Output Enable (OE) Selection Table
OE1 OE2 Bank1 (CLK0 & CLK3) Bank2 (CLK1 & CLK2)
00
Hi-Z
Hi-Z
01
Hi-Z
Running
10
Running
Hi-Z
11
Running
Running
Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to
allow for optimized noise isolation between the two banks. Each bank provides two synchronous
outputs generated by a common PLL:
Bank1 is composed of outputs CLK0 and CLK3
Bank2 is composed of outputs CLK1 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS,
LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the
frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off
in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from
2.3MHz to 170MHz on LVCMOS outputs.
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different
supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should
have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.
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DSC400
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3 Page

DSC400 pdf
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVPECL Outputs6
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time4
Rise Time
Fall Time
Frequency
Output Duty Cycle
VOH
VOL
tR
tF
f0
SYM
RL=50Ω
Single-Ended
20% to 80%
RL=50Ω
Single Frequency
Differential
Supply Current IO2
IDDio
Per output at 125MHz
Period Jitter5
JPER CLK(0:3) = 156.25 MHz
200kHz to 20MHz @156.25MHz
Integrated Phase Noise
JPH 100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
Notes:
5. Period Jitter includes crosstalk from adjacent output
6. LVPECL applicable to ext. commercial temperature only
VDD-1.08
-
2.3
48
800
250
35
2.5
0.25
0.38
1.7
-
VDD-1.55
V
mV
ps
460
52
38
2
MHz
%
mA
psRMS
psRMS
LVPECL: Typical Termination Scheme
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DSC400
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Un datasheet est un document fourni par le constructeur du composant, où figurent toutes les données techniques sur le produit: puissance dissipée, courant maximal, tension de seuil, tension de claquage, température de stockage, etc. Ils sont en général fournis gratuitement, et se présentent très régulièrement sous la forme d'un document pdf.


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