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PDF GM72V66841ELT Fiche technique ( Data sheet )

Numéro de référence GM72V66841ELT
Description 2M x 8-Bit x 4 Bank SDRAM
Fabricant Hynix Semiconductor 
Logo Hynix Semiconductor Logo 



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GM72V66841ELT Datasheet, Description
Description
The GM72V66841ET/ELT is a synchronous
dynamic random access memory comprised of
67,108,864 memory cells and logic including
input and output circuits operating synchronously
by referring to the positive edge of the externally
provided Clock.
The GM72V66841ET/ELT provides four banks
of 2,097,152 word by 8 bit to realize high
bandwidth with the Clock frequency up to 143
Mhz.
Features
* PC133/PC100/PC66 Compatible
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
* 3.3V single Power supply
* LVTTL interface
* Max Clock frequency
143/133/125/100MHz
* 4,096 refresh cycle per 64 ms
* Two kinds of refresh operation
Auto refresh / Self refresh
* Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
* Programmable CAS latency : 2/3
* 4 Banks can operate independently or
simultaneously
* Burst read/burst write or burst read/single
write operation capability
* Input and output masking by DQM input
* One Clock of back to back read or write
command interval
* Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
* JEDEC Standard 54Pin 400mil TSOP II
Package
GM72V66841ET/ELT
2,097,152 WORD x 8 BIT x 4 BANK
SYNCHRONOUS DYNAMIC RAM
Pin Configuration
VCC 1
DQ0 2
VCCQ 3
NC 4
DQ1 5
VSSQ 6
NC 7
DQ2 8
VCCQ 9
NC 10
DQ3 11
VSSQ 12
NC 13
VCC 14
NC 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0/A13 20
BA1/A12 21
A10,AP 22
A0 23
A1 24
A2 25
A3 26
VCC 27
JEDEC STANDARD
400 mil 54 PIN TSOP II
(TOP VIEW)
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VCCQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VCCQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Pin Name
CLK
CKE
CS
RAS
CAS
WE
A0~A9,A11
A10 / AP
BA0/A13
~BA1/A12
DQ0~DQ7
DQM
VCCQ
VSSQ
VCC
VSS
NC
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Address input or Auto Precharge
Bank select
Data input / Data output
Data input / output Mask
VCC for DQ
VSS for DQ
Power for internal circuit
Ground for internal circuit
No Connection
This document is a general product description and is subject to change without notice. Hynix semiconductor does not a-s1s-ume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
GM72V66841ELT Fiche technique
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pin relative to VSS
VT
Supply voltage relative to VSS
VCC
Short circuit output current
IOUT
Power dissipation
PT
Operating temperature
Topr
Storage temperature
Tstg
Notes : 1. Respect to VSS
GM72V66841ET/ELT
Value
-0.5 to Vcc+0.5
( 4.6 (max))
-0.5 to +4.6
50
1.0
0 to +70
-55 to +125
Unit
V
V
mA
W
Note
1
1
Recommended DC Operating Conditions (Ta = 0 to + 70 )
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol Min Max Unit
VCC, VCCQ
3.0
3.6
V
VSS, VSSQ
0
0V
VIH
2.0 Vcc+0.3
V
VIL -0.3 0.8 V
Notes : 1. All voltage referred to VSS.
2. VIH (max) = 5.6V for pulse width
3. VIL (min) = -2.0V for pulse width
3ns
3ns
Note
1
1, 2
1,3
Rev. 1.1/Apr.01
-3-

3 Page

GM72V66841ELT pdf
GM72V66841ET/ELT
AC Characteristics (Ta = 0 to 70 , VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
Parameter
-7
- 75
-8
- 7K
- 7J
Symbol
Unit Notes
Min Max Min Max Min Max Min Max Min Max
System clock (CL=2)
cycle time
(CL=3)
tCK
tCK
10 - 10 - 10 - 10 - 15 -
7 - 7.5 - 8 - 10 - 10 -
ns
1
CLK high pulse width
tCKH 2.5 - 2.5 - 3 - 3 - 3 - ns 1
CLK low pulse width
tCKL 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Access time
from CLK
(CL=2)
(CL=3)
tAC
tAC
-6-6-6-6-8
ns 1, 2
- 5.4 - 5.4 - 6 - 6 - 6
Data-out hold time
CLK to Data-out low
impedance
CLK to Data-out
high impedance
( CL = 2,3 )
Data-in setup time
tOH 2.7 - 2.7 - 3 - 3 - 3 - ns 1, 2
tLZ 1.5 - 1.5 - 2 - 2 - 2 - ns 1, 2, 3
tHZ - 5.4 - 5.4 - 6 - 6 - 6 ns 1, 4
tDS 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Data-in hold time
tDH 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Address setup time
tAS 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Address hold time
tAH 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CKE setup time
CKE setup time for
power down exit
CKE hold time
tCES 1.5 - 1.5 - 2 - 2 - 2 - ns 1, 5
tCESP 1.5 - 1.5 - 2 - 2 - 2 - ns
1
tCEH 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Command (CS, RAS,
CAS, WE, DQM)
setup time
tCS 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Command (CS, RAS,
CAS, WE, DQM)
hold time
tCH 0.8 - 0.8 - 1 - 1 - 1 - ns
Ref/Active to Ref/Active
command period
tRC
62 - 65 - 68 - 70 - 70 -
ns
Active to Precharge
command period
tRAS
42 120000 45 120000 48 120000 50 120000 50 120000 ns
Active command to
column command
tRCD 20 - 20 - 20 - 20 - 20 - ns
(same bank)
Precharge to active
command period
tRP 20 - 20 - 20 - 20 - 20 - ns
1
1
1
1
1
Rev. 1.1/Apr.01
-6-

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Un datasheet est un document fourni par le constructeur du composant, où figurent toutes les données techniques sur le produit: puissance dissipée, courant maximal, tension de seuil, tension de claquage, température de stockage, etc.


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