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Numéro de référence ADuM4135
Description High Voltage Isolated IGBT Gate Driver
Fabricant Analog Devices 
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ADuM4135 Datasheet, Description
Data Sheet
Single-/Dual-Supply, High Voltage Isolated
IGBT Gate Driver with Miller Clamp
ADuM4135
FEATURES
GENERAL DESCRIPTION
4 A peak drive output capability
Output power device resistance: <1 Ω
Desaturation protection
Isolated desaturation fault reporting
Soft shutdown on fault
Miller clamp output with gate sense input
Isolated fault and ready functions
Low propagation delay: 55 ns typical
Minimum pulse width: 50 ns
The ADuM4135 is a single-channel gate driver specifically
optimized for driving insulated gate bipolar transistors (IGBTs).
Analog Devices, Inc., iCoupler® technology provides isolation
between the input signal and the output gate drive.
The ADuM4135 includes a Miller clamp to provide robust
IGBT turn-off with a single-rail supply when the gate voltage
drops below 2 V. Operation with unipolar or bipolar secondary
supplies is possible, with or without the Miller clamp operation.
Operating temperature range: −40°C to +125°C
The Analog Devices chip scale transformers also provide
Output voltage range to 30 V
isolated communication of control information between the
Input voltage range from 2.3 V to 6 V
high voltage and low voltage domains of the chip. Information
Output and input undervoltage lockout (UVLO)
on the status of the chip can be read back from dedicated
Creepage distance: 7.8 mm minimum
outputs. Control of resetting the device after a fault on the
100 kV/µs common-mode transient immunity (CMTI)
20 year lifetime for 600 V rms or 1092 V dc working voltage
Safety and regulatory approvals (pending)
5 kV ac for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (reinforced/basic)
APPLICATIONS
secondary is performed on the primary side of the device.
Integrated onto the ADuM4135 is a desaturation detection
circuit that provides protection against high voltage short-
circuit IGBT operation. The desaturation protection contains
noise reducing features such as a 300 ns masking time after a
switching event to mask voltage spikes due to initial turn-on.
An internal 500 µA current source allows low device count and
the internal blanking switch allows the addition of an external
MOSFET/IGBT gate drivers
current source if more noise immunity is needed.
PV inverters
Motor drives
Power supplies
The secondary UVLO is set to 11 V with common IGBT
threshold levels taken into consideration.
FUNCTIONAL BLOCK DIAGRAM
VSS1 1
VI+ 2
VI3
READY 4
1
FAULT 5
1
ADuM4135
UVLO
MASTER
LOGIC
PRIMARY
ENCODE
RESET 6
VDD1 7
VSS1 8
1
1
1
DECODE
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE
ISOLATED FROM EACH OTHER.
TSD
CLAMP
LOGIC
2V
2
DECODE
ENCODE
MASTER
LOGIC
SECONDARY
2
9V
2
UVLO
16 VSS2
2
15 GATE_SENSE
14 VOUT_ON
13 VDD2
12 VOUT_OFF
11 GND2
10 DESAT
9 VSS2
2
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM4135 Fiche technique
Data Sheet
ADuM4135
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to VSS1. High-side voltages referenced to GND2, 2.3 V ≤ VDD1 ≤ 6 V, 12 V ≤ VDD2 ≤ 30 V, and TJ = −40°C to +125°C.
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are
at TJ = 25°C, VDD1 = 5.0 V, and VDD2 = 15 V.
Table 1.
Parameter
DC SPECIFICATIONS
High-Side Power Supply
Input Voltage
VDD2
VSS2
Input Current, Quiescent
VDD2
VSS2
Logic Supply
VDD1 Input Voltage
Input Current
Output Low
Output High
Logic Inputs (VI+, VI−, RESET)
Input Current (VI+, VI− Only)
Logic High Input Voltage
Logic Low Input Voltage
Symbol Min
VDD2
VSS2
IDD2 (Q)
ISS2 (Q)
VDD1
IDD1
12
−15
2.3
II −1
VIH 0.7 ×
VDD1
3.5
VIL
RESET Internal Pull-Down
UVLO
VDD1 Positive Going Threshold
VDD1 Negative Going Threshold
VDD1 Hysteresis
VDD2 Positive Going Threshold
VDD2 Negative Going Threshold
VDD2 Hysteresis
FAULT Pull-Down FET Resistance
READY Pull-Down FET Resistance
Desaturation (DESAT)
Desaturation Detect Comparator Voltage
Internal Current Source
Thermal Shutdown
TSD Positive Edge
TSD Hysteresis
Miller Clamp Voltage Threshold
Internal NMOS Gate Resistance
Internal PMOS Gate Resistance
RRESET_PD
VVDD1UV+
VVDD1UV−
VVDD1UVH
VVDD2UV+
VVDD2UV−
VVDD2UVH
RFAULT
_PD_FET
RRDY_PD_FET
2.0
10.4
VDESAT, TH
IDESAT_SRC
8.73
481
TTSD_POS
TTSD_HYST
VCLP_TH
RDSON_N
1.75
RDSON_P
Typ Max
30
0
3.62 4.37
4.82 6.21
6
1.78 2.17
4.78 5.89
+0.01 +1
0.29 ×
VDD1
1.5
300
2.23
2.135
0.095
11.5
11.1
0.4
11
2.3
12.0
50
11 50
9.2 9.61
537 593
155
20
2 2.25
315 625
318 625
471 975
479 975
Unit Test Conditions/Comments
V VDD2 − VSS2 ≤ 30 V
V
Ready high
mA
mA
V
mA Output signal low
mA Output signal high
µA
V 2.3 V ≤ VDD1 − VSS1 ≤ 5 V
V VDD1 − VSS1 > 5 V
V 2.3 V ≤ VDD1 − VSS1 ≤ 5 V
V VDD1 − VSS1 > 5 V
V
V
V
V
V
V
Ω Tested at 5 mA
Ω Tested at 5 mA
V
µA
°C
°C
V Referenced to VSS2
mΩ Tested at 250 mA
mΩ Tested at 1 A
mΩ Tested at 250 mA
mΩ Tested at 1 A
Rev. B | Page 3 of 17

3 Page

ADuM4135 pdf
ADuM4135
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm =
1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
VIO = 500 V
Symbol Characteristic
VIORM
Vpd (m)
I to IV
I to III
I to II
40/105/21
2
849
1592
Vpd (m)
Vpd (m)
VIOTM
VIOSM
1274
1019
8000
8000
TS 150
PS 2.77
RS >109
Unit
V peak
V peak
V peak
V peak
V peak
V peak
°C
W
Ω
3.0
2.5
2.0
1.5
1.0
0.5
0
0 50 100 150 200
AMBIENT TEMPERATURE (°C)
Figure 2. ADuM4135 Thermal Derating Curve, Dependence of Safety
Limiting Values on Case Temperature, per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Operating Temperature Range (TA)
Supply Voltages
VDD11
VDD22
VDD2 − VSS22
VSS22
Input Signal Rise/Fall Time
Static Common-Mode Transient
Immunity3
Dynamic Common-Mode Transient
Immunity4
Value
−40°C to +125°C
2.3 V to 6 V
12 V to 30 V
12 V to 30 V
−15 V to 0 V
1 ms
−100 kV/µs to
+100 kV/µs
−100 kV/µs to
+100 kV/µs
1 Referenced to VSS1.
2 Referenced to GND2.
3 Static common-mode transient immunity is defined as the largest dv/dt
between VSS1 and VSS2, with inputs held either high or low, such that the
output voltage remains either above 0.8 × VDD2 for output high or 0.8 V for
output low. Operation with transients above recommended levels can cause
momentary data upsets.
4 Dynamic common-mode transient immunity is defined as the largest dv/dt
between VSS1 and VSS2 with the switching edge coincident with the transient
test pulse. Operation with transients above recommended levels can cause
momentary data upsets.
Rev. B | Page 6 of 17

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