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Numéro de référence ADuM4150
Description SPIsolator Digital Isolator
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ADuM4150 Datasheet, Description
Data Sheet
5 kV, 6-Channel, SPIsolator Digital
Isolator for SPI with Delay Clock
ADuM4150
FEATURES
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SOIC_IC with 8.3 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
GENERAL DESCRIPTION
The ADuM41501 is a 6-channel, SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
MI/SO, and SS SPI bus signals supports SPI clock rates of up to
17 MHz. These channels operate with 13 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
The ADuM4150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 µs of jitter.
The ADuM4150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
FUNCTIONAL BLOCK DIAGRAM
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM4150
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VOB 8
DCLK 9
GND1 10
CONTROL
BLOCK
CLK
DELAY
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
Figure 1.
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VIB
12 NIC
11 GND2
Table 1. Related Products
Product
ADuM3150
ADuM3151/ADuM3152/
ADuM3153
ADuM3154
ADuM4151/ADuM4152/
ADuM4153
ADuM4154
Description
3.75 kV, high speed, clock delayed
SPIsolator
3.75 kV, multichannel SPIsolator
3.75 kV, multiple slave SPIsolator
5 kV, multichannel SPIsolator
5 kV, multiple slave SPIsolator
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM4150 Fiche technique
Data Sheet
ADuM4150
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended
operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
Jitter, High Speed
DCLK3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx4 Minimum Input Skew5
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
tPHL, tPLH
PWD
PW
DCLKERR
JDCLK
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
A Grade
Min Typ Max
12.5
1
10
40
24
2
2
21
12.5
1.5
1
40
24
2
40
50
3
12
0 4.5 12
1
250
0.1 2.6
4
2.5
10
B Grade
Min Typ Max
12
12.5
1
17
40
13
2
2
21
12.5
10
1
40
24
2
40
35
3
12
1 5.5 12
1
250
0.1 2.6
4
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
tPMCLK + tPSO + 3 ns
|tPLH − tPHL|
Within PWD limit
tPDCLK − (tPMCLK + tPSO)
Within PWD limit
50% input to 50% output
Within PWD limit
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4 VIx = VIA or VIB.
5 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. B | Page 3 of 21

3 Page

ADuM4150 pdf
ADuM4150
Data Sheet
Table 5. For All Grades1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current per High Speed Channel
Dynamic Input
Dynamic Output
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol Min
IDD1
IDD2
IDD1
IDD2
Typ Max
3.5 6
4.9 8
9.5 20
8 16
Unit
mA
mA
mA
mA
Test Conditions/Comments
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
VIH
VIL
VIHYST
II
0.7 × VDDx
−1
500
+0.01
0.3 × VDDx
+1
V
V
mV
µA
0 V ≤ VINPUT ≤ VDDx
VOH
VOL
UVLO
IDDI(D)
IDDO(D)
IDD1(Q)
IDD2(Q)
tR/tF
|CM|
VDDx − 0.1
VDDx − 0.4
5.0
4.8
0.0
0.2
2.6
0.1
0.4
0.086
0.019
2.9
4.6
2.5
25 35
V IOUTPUT = −20 µA, VINPUT = VIH
V IOUTPUT = −4 mA, VINPUT = VIH
V IOUTPUT = 20 µA, VINPUT = VIL
V IOUTPUT = 4 mA, VINPUT = VIL
V
mA/Mbps
mA/Mbps
mA
mA
ns
kV/µs
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 6 of 21

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