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Numéro de référence ADuM240D
Description 5.0 kV rms Quad Digital Isolators
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ADuM240D Datasheet, Description
5.0 kV rms Quad Digital Isolators
Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E
FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
8000 V peak reinforced surge isolation voltage
CQC certification per GB4943.1-2011
Backward compatibility
ADuM240E1/ADuM241E1/ADuM242E1 pin compatible
with ADuM2400/ADuM2401/ADuM2402
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, SOIC package
Qualified for automotive applications
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM240D/ADuM240E/ADuM241D/ADuM241E/
ADuM242D/ADuM242E1 are quad-channel digital isolators
based on Analog Devices, Inc., iCoupler® technology. Combining
high speed, complementary metal-oxide semiconductor (CMOS)
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices and other
integrated couplers. The maximum propagation delay is 13 ns
with a pulse width distortion of less than 3 ns at 5 V operation.
Channel matching is tight at 3.0 ns maximum.
The ADuM240D/ADuM240E/ADuM241D/ADuM241E/
ADuM242D/ADuM242E data channels are independent and
are available in a variety of configurations with a withstand
voltage rating of 5.0 kV rms (see the Ordering Guide). The
devices operate with the supply voltage on either side ranging
from 1.8 V to 5 V, providing compatibility with lower voltage
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1 ADuM240D/ADuM240E 16 VDD2
GND1 2
VIA 3
ENCODE
DECODE
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC 5
ENCODE
DECODE
12 VOC
VID 6
ENCODE
DECODE
11 VOD
DISABLE1/NIC 7
GND1 8
10 NIC/VE2
9 GND2
NOTES
1. NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
2. PIN 7 IS DISABLE1 AND PIN 10 IS NIC FOR THE ADuM240D, AND
PIN 7 IS NIC AND PIN 10 IS VE2 FOR THE ADuM240E.
Figure 1. ADuM240D/ADuM240E Functional Block Diagram
VDD1 1 ADuM241D/ADuM241E 16 VDD2
GND1 2
VIA 3
ENCODE
DECODE
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC 5
ENCODE
DECODE
12 VOC
VOD 6
DECODE
ENCODE
11 VID
DISABLE1/VE1 7
GND1 8
10 DISABLE2/VE2
9 GND2
NOTES
1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM241D,
AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM241E.
Figure 2. ADuM241D/ADuM241E Functional Block Diagram
VDD1 1
GND1 2
VIA 3
ADuM242D/ADuM242E
ENCODE
DECODE
16 VDD2
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VOC 5
DECODE
ENCODE
12 VIC
VOD 6
DECODE
ENCODE
11 VID
DISABLE1/VE1 7
GND1 8
10 DISABLE2/VE2
9 GND2
NOTES
1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM242D,
AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM242E.
Figure 3. ADuM242D/ADuM242E Functional Block Diagram
systems as well as enabling voltage translation functionality
across the isolation barrier.
Unlike other optocoupler alternatives, dc correctness is ensured in
the absence of input logic transitions. Two different fail-safe options
are available by which the outputs transition to a predetermined
state when the input power supply is not applied or the inputs are
disabled. The ADuM240E1/ADuM241E1/ ADuM242E1 are pin
compatible with the ADuM2400/ ADuM2401/ADuM2402.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM240D Fiche technique
Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
VE2 Enable Input Pull-Up Current
DISABLE1 Input Pull-Down Current
Tristate Output Current per Channel
Quiescent Supply Current
ADuM240D/ADuM240E
ADuM241D/ADuM241E
ADuM242D/ADuM242E
Dynamic Supply Current
Dynamic Input
Dynamic Output
Symbol Min
Typ Max Unit
Test Conditions/Comments
PW 6.6
150
tPHL, tPLH 4.8
7.2 13
PWD
0.5 3
1.5
tPSK 6.1
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the
same temperature, voltage, and load
tPSKCD
tPSKOD
0.5 3.0
0.5 3.0
490
70
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
VIH 0.7 × VDDx
VIL
V
0.3 × VDDx V
VOH VDDx − 0.1 VDDx
VDDx − 0.4 VDDx − 0.2
VOL 0.0 0.1
0.2 0.4
II −10 +0.01 +10
IPU −10 −3
IPD 9 15
IOZ −10 +0.01 +10
V
V
V
V
μA
μA
μA
μA
IOx2 = −20 μA, VIx = VIxH3
IOx2 = −4 mA, VIx = VIxH3
IOx2 = 20 μA, VIx = VIxL4
IOx2 = 4 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
VE2 = 0 V
DISABLE1 = VDDx
0 V ≤ VOx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDDI (D)
IDDO (D)
1.2 2.2
2.0 2.72
12.0 20.0
2.0 2.92
mA
mA
mA
mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
1.6 2.46
1.9 2.62
10.0 17.0
6.0 10.0
mA
mA
mA
mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0(E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
1.6 2.46 mA
1.6 2.46 mA
7.0 11.5 mA
7.0 11.5 mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
0.01 mA/Mbps Inputs switching, 50% duty cycle
0.02 mA/Mbps Inputs switching, 50% duty cycle
Rev. A | Page 3 of 26

3 Page

ADuM240D pdf
ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E Data Sheet
Parameter
Symbol Min
Typ Max Unit
Test Conditions/Comments
Undervoltage Lockout
UVLO
Positive VDDx Threshold
VDDxUV+
1.6
V
Negative VDDx Threshold
VDDxUV−
1.5
V
VDDx Hysteresis
VDDxUVH
0.1
V
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
Common-Mode Transient Immunity7 |CMH|
75
2.5
100
ns
kV/μs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML|
75
100
kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, or D.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 is the ADuM240E0/ADuM241E0/ADuM242E0 models, D0 is the ADuM240D0/ADuM241D0/ADuM242D0 models, E1 is the ADuM240E1/ADuM241E1/ADuM242E1
models, and D1 is the ADuM240D1/ADuM241D1/ADuM242D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps
Parameter
Symbol
Min Typ Max
SUPPLY CURRENT
ADuM240D/ADuM240E
Supply Current Side 1
IDD1
6.6 9.8
Supply Current Side 2
IDD2
2.0 3.7
ADuM241D/ADuM241E
Supply Current Side 1
IDD1
5.65 10.1
Supply Current Side 2
IDD2
3.9 6.65
ADuM242D/ADuM242E
Supply Current Side 1
IDD1
4.3 7.7
Supply Current Side 2
IDD2
5.0 8.4
25 Mbps
Min Typ Max
7.4 11.2
3.5 5.5
6.65 10.5
5.2 8.0
5.6 9.0
6.2 9.6
100 Mbps
Min Typ Max
10.7 15.9
8.2 11.6
10.4 14.9
9.4 12.8
9.1 13
9.8 13.7
Unit
mA
mA
mA
mA
mA
mA
Rev. A | Page 6 of 26

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