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PDF ADLD8403 Fiche technique ( Data sheet )

Numéro de référence ADLD8403
Description Dual-Port ADSL/ADSL2+ Line Driver
Fabricant Analog Devices 
Logo Analog Devices Logo 



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ADLD8403 Datasheet, Description
Data Sheet
Ultralow Power, Adaptive Linear Power,
Dual-Port ADSL/ADSL2+ Line Driver
ADLD8403
FEATURES
2 differential DSL channels comprising current feedback,
high output current amplifiers with integrated feedback
resistors plus biasing network
Ideal for use as ADSL/ADSL2+ dual-channel central office
(CO) line drivers
Low power consumption using Class H technology
Single 12.5 V supply operation
20.4 dBm line power, 1:1 transformer
Less than 600 mW per channel total power dissipation
while driving 20.4 dBm (includes 110 mW line power)
Less than 275 mW per channel total power dissipation
while driving 14.5 dBm (including line power)
High output voltage and current drive
43.4 V differential output voltage swing
Low distortion
−65 dBc typical multitone power ratio (MTPR) at 20.4 dBm,
26 kHz to 2.2 MHz
Low cost protection components enable ITU-T-K20 and
GR-1089 compliance
APPLICATIONS
ADSL/ADSL2+ CO line drivers
INTERNAL SCHEMATIC
VCC VCCP
INPA
VCOM_A
INNA
VCC
4kΩ
4kΩ
AV = 13V/V
VOPA
VONA
VEEP
Figure 1. Channel A Internal Schematic
GENERAL DESCRIPTION
The ADLD8403 comprises two differential, high output current,
low power consumption operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver can deliver
20.4 dBm to a line while compensating for losses due to hybrid
insertion and back termination resistors. The ADLD8403 uses
the Analog Devices, Inc., second generation Adaptive Linear
Power™ (Class H) architecture to achieve unprecedented power
efficiency using a single power supply. Additional functionality
allows the shutdown of pumps for enhanced power savings for
line powers of less than 14.5 dBm. This functionality yields the
smallest printed circuit board (PCB) footprint and lowest total
cost of ownership.
The low power consumption, high output current, high
output voltage swing, and robust thermal packaging enable
the ADLD8403 to be the CO line driver in ADSL and other
xDSL systems.
The ADLD8403 is available in a 4 mm × 4 mm, 20-lead LFCSP.
18
14
10
6
2
–2
VOPA
VONB
VONA
VCCP
VOPB
–6
VEEP
0 1 2 3 4 5 6 7 8 9 10
TIME (µs)
Figure 2. Outputs and Pumps Time Domain Response, Typical ADSL/ADSL2+
Application Circuit, VCC = 12.5 V, POUT = 20.4 dBm, Crest Factor = 5.45
Rev. C
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADLD8403 Fiche technique
ADLD8403
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Internal Schematic............................................................................ 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Absolute Maximum Ratings............................................................ 4 
Thermal Resistance ...................................................................... 4 
Maximum Power Dissipation ..................................................... 4 
ESD Caution.................................................................................. 4 
Pin Configuration and Function Descriptions............................. 5 
Typical Performance Characteristics ............................................. 6 
REVISION HISTORY
9/14—Revision C: Initial Version
Data Sheet
Theory of Operation .........................................................................7 
Applications Information .................................................................8 
Supplies, Grounding, and Layout................................................8 
Power Management ......................................................................8 
Dynamic Supplies..........................................................................8 
Typical ADSL/ADSL2+ Application...........................................8 
Multitone Power Ratio (MTPR)..................................................9 
Lightning and AC Power Fault ....................................................9 
Outline Dimensions ....................................................................... 10 
Ordering Guide .......................................................................... 10 
Rev. C | Page 2 of 10

3 Page

ADLD8403 pdf
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADLD8403
INPA 1
INNA 2
PD_PMP 3
INNB 4
INPB 5
ADLD8403
TOP VIEW
(Not to Scale)
15 CAPP
14 VCCP
13 GND
12 VEEP
11 CAPN
NOTES
1. CONNECT THE EXPOSED PAD TO THE GND PLANE FOR
THE THERMAL PATH. NO INTERNAL ELECTRICAL
CONNECTION EXISTS.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 INPA
Port A Input P
2 INNA Port A Input N
3 PD_PMP Control for Port A and Port B Pumps
4 INNB Port B Input N
5 INPB
Port B Input P
6
VCOM_B
Port B VCOM
7 PD_B Port B Shutdown
8
VONB
Port B Output N
9 VOPB Port B Output P
10 GND
Ground
11 CAPN
Pump Capacitor Negative
12 VEEP
Dynamic Negative Supply
13 GND
Ground
14 VCCP
Dynamic Positive Supply
15 CAPP
Pump Capacitor Positive
16 VCC
Positive Power Supply
17 VOPA
Port A Output P
18 VONA Port A Output N
19 PD_A
Port A Shutdown
20
VCOM_A
Port A VCOM
EPAD
Exposed Pad. Connect the exposed pad to the GND plane for the thermal path. No internal electrical connection exists.
Rev. C | Page 5 of 10

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