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PDF AD9531 Fiche technique ( Data sheet )

Numéro de référence AD9531
Description 3-Channel Clock Generator
Fabricant Analog Devices 
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AD9531 Datasheet, Description
Data Sheet
3-Channel Clock Generator, 24 Outputs
AD9531
FEATURES
3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3)
Jitter performance: 0.462 ps rms typical
PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth
Loss of reference and lock detection for each PLL
Pin-configurable common frequency translations
Automatic synchronization of all outputs on power-up
Manual output synchronization capability
Package available in an 88-lead LFCSP
PLL1 details
Fractional-N/integer-N modes
Optional external VCXO
Fixed delay mode for constant static phase offset
2 reference clock inputs
Input format: differential/single-ended
Frequency range: 9.5 MHz to 260 MHz
Reference switching: manual/automatic
10 ultralow jitter HSTL/CMOS outputs up to 400 MHz
PLL2 details
Integer-N mode (1 reference clock input)
Input format: differential/single-ended/crystal1
Frequency range: 9.5 MHz to 250 MHz
12 HSTL/CMOS outputs up to 400 MHz
PLL3 details
Integer-N mode (1 reference clock input)
Frequency range: 9.5 MHz to 100 MHz
Input format: differential/crystal (supports a 25 MHz to
50 MHz AT-cut quartz crystal resonator)
2 HSTL/LVDS/CMOS outputs to 400 MHz/150 MHz
(differential/CMOS)
APPLICATIONS
Radio equipment controller clocking
Low jitter/phase noise clock generation and distribution
Clock generation and translation for SONET, 10GE, 10G FC,
and other 10 Gbps protocols
40 Gbps/100 Gbps networking line cards, including SONET,
synchronous ethernet, OTU2/3/4
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
Ethernet line cards, switches, and routers
SATA and PCI-express
GENERAL DESCRIPTION
The AD9531 provides a multioutput clock generator function
and three on-chip phase-locked loop (PLL) cores with SPI
programmable output frequencies and formats.
PLL1 provides two reference inputs and 10 outputs and includes
four user selectable loop configurations. The PLL has a fully
integrated loop filter requiring only a single external capacitor
(or a series RC network). PLL1 provides a wide range of output
frequencies up to 400 MHz and is capable of operating with an
external voltage controlled crystal oscillator (VCXO) and loop
filter, instead of the integrated voltage controlled oscillator
(VCO) and loop filter.
PLL2 is an integer-N PLL providing a single reference input and
12 outputs. PLL2 synthesizes output frequencies up to 400 MHz
from the REF2_x source and synchronizes the output clocks to
the input reference.
PLL3 provides a single reference input and two outputs. PLL3
synthesizes output frequencies up to 400 MHz from the REF3_x
source and synchronizes the output clocks to input reference.
The AD9531 is available in an 88-lead LFCSP and is specified
over the −40°C to +85°C operating temperature range.
Throughout this data sheet, multifunction pins, such as
LOR/M4, are referred to either by the entire pin name or by a
single function of the pin (for example, LOR, when only that
function is relevant). In other cases, the text and figures of this
data sheet contain references to a channel rather than a pin. For
example, REF_A refers to the REF_A channel rather than the
REF_AP and REF_AN pins. Likewise, OUT3_1 refers to
Channel 1 of PLL3 rather than the OUT3_1P and OUT3_1N pins.
Additionally, an abbreviated notation for a pin pair replaces an
explicit reference to a each pin (for example, REF_Ax signifies
the REF_AN and REF_AP pins.).
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9531 Fiche technique
Data Sheet
PLL2 Registers .............................................................................69 
PLL3 Registers .............................................................................75 
ROM Profile Data............................................................................77 
ROM Profile 0 to ROM Profile 15 ............................................77 
ROM Profile 16 to ROM Profile 31 ..........................................78 
ROM Profile 32 to ROM PRofile 47 .........................................80 
ROM Profile 48 to ROM Profile 63 ..........................................82 
Thermal Performance.....................................................................84 
REVISION HISTORY
1/16—Revision 0: Initial Version
AD9531
Thermal Resistance.....................................................................84 
Applications Information...............................................................85 
Interfacing to the Multifunction Pins ......................................85 
Interfacing to the RFIN1_x Pins ...............................................86 
Driving REF2 or REF3 with 3.3 V CMOS Logic ....................87 
Using REF2 or REF3 with a Crystal Resonator ......................87 
Outline Dimensions........................................................................88 
Ordering Guide ...............................................................................88 
Rev. 0 | Page 3 of 88

3 Page

AD9531 pdf
AD9531
Data Sheet
Parameter
Case 4
1.8 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
DVDD Pin
3.3 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
Case 5
1.8 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
DVDD Pin
3.3 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
INCREMENTAL SUPPLY CURRENT
PLL1, External VCXO Configuration
1.8 V Supply (PLL1 Pins)
3.3 V Supply (PLL1 Pins)
PLL3, Dual Loop Configuration
1.8 V Supply (PLL3 Pins)
3.3 V Supply (PLL3 Pins)
Min Typ
Max Unit Test Conditions/Comments
PLL1: off; PLL3: 3.3 V, CMOS input at 25 MHz, OUT3_0 and OUT3_1 at
125 MHz (1.8 V CMOS and HSTL, respectively); PLL2: off
6 mA
19 mA
72 mA
0.3 mA
3.2 mA
1.3 mA
0.1 mA
PLL1: differential input at 122.88 MHz, HSTL output at 122.88 MHz, all
outputs active, internal VCO; PLL2: 3.3 V, CMOS input at 50 MHz, HSTL
output at 156.25 MHz, all outputs active; PLL3: 3.3 V, CMOS input at
25 MHz, OUT3_0 and OUT3_1 at 125 MHz (1.8 V CMOS and HSTL,
respectively)
270 mA
280 mA
72 mA
0.3 mA
34 mA
23 mA
0.1 mA
−22 mA
−27 mA
36 mA
0 mA
POWER DISSIPATION
Table 3.
Parameter
POWER CONSUMPTION
Case 1
1.8 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
DVDD Pin
3.3 V Supply
PLL1 Pins
PLL2 Pins
PLL3 Pins
Min Typ Max Unit Test Conditions/Comments
Does not include power dissipated in the external resistors
PLL1: off; PLL2: off; PLL3 off
11 mW
35 mW
2.5 mW
0.5 mW
11 mW
4.0 mW
0.3 mW
Rev. 0 | Page 6 of 88

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