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Numéro de référence ADP3121JCPZ-RL
Description 12V MOSFET Driver
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ADP3121JCPZ-RL Datasheet, Description
ADP3121
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3121 is a dual, high voltage MOSFET driver optimized for
driving two Nchannel MOSFETs, the two switches in a nonisolated
synchronous buck power converter. Each driver is capable of driving a
3000 pF load with a 20 ns propagation delay and a 15 ns transition
time.
One of the drivers can be bootstrapped and is designed to handle the
high voltage slew rate associated with floating highside gate drivers.
The ADP3121 includes overlapping drive protection to prevent
shootthrough current in the external MOSFETs.
The OD pin shuts off both the highside and the lowside
MOSFETs to prevent rapid output capacitor discharge during system
shutdown.
The ADP3121 is specified over the commercial temperature range
of 0°C to 85°C and is available in 8lead SOIC_N and 8lead LFCSP
packages.
Features
AllInOne Synchronous Buck Driver
Bootstrapped HighSide Drive
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
Overvoltage Protection
OD for Disabling the Driver Outputs
Meets CPU VR Requirement when Used with FlexModet
Controller
These are PbFree Devices
Typical Applications
Multiphase Desktop CPU Supplies
Single Supply Synchronous Buck Converters
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MARKING
DIAGRAMS
8 SO8
1
D SUFFIX
CASE 75107
8
P3121
ALYW G
G
P3121A = Device Code
1
AL = Assembly Location
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
8
1
LFCSP8
MN SUFFIX
CASE 932AF
L7Q
#YWW
L7Q = Device Code
# = PbFree Package
Y = Year
WW = Work Week
PIN ASSIGNMENT
BST
IN
OD
VCC
DRVH
SWN
PGND
DRVL
ORDERING INFORMATION
Device
Package
Shipping
ADP3121JRZRL SOIC_N 2500/Tape & Reel
(PbFree)
ADP3121JCPZRL LFCSP_VD 5000/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
February, 2010 Rev. 1
1
Publication Order Number:
ADP3121/D
ADP3121JCPZ-RL Fiche technique
ADP3121
MAXIMUM RATINGS
Rating
Value
Unit
qJA, SOIC_N
2Layer Board
4Layer Board
°C/W
123
90
qJA, LFCSP_VD (Note 1)
4Layer Board
°C/W
64.3
Operating Ambient Temperature Range
0 to 85
°C
Junction Temperature Range
0 to 150
°C
Storage Temperature Range
65 to +150
°C
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
°C
300
215
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min. 2layer board, 1 in2 Cu, 1 oz thickness. 60180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
ABSOLUTE MAXIMUM RATINGS (Note 2)
Pin Symbol
Pin Name
VCC
GND
Main supply voltage input
Ground
Vmax
15 V
0V
Vmin
0.3 V
0V
BST Bootstrap Supply Voltage Input
DC
<200 ns
BST to SW
VCC + 15
+35
+15
0.3 V
SW Switching Node (Bootstrap Supply Return)
DC
<200 ns
+15
+25 V
5 V
10 V
DRVH
HighSide Driver Output
DC
<20 ns
<200 ns
BST + 0.3 V
BST + 2.0 V
BST + 0.3 V
SW 0.3 V
SW 2.0 V
SW 2.0 V
DRVL
IN
LowSide Driver Output
DC
<20 ns
<200 ns
DRVH and DRVL Control Input
VCC + 0.3 V
VCC + 2.0 V
VCC + 0.3 V
6.5 V
0.3 V
2.0 V
2.0 V
0.3 V
OD Outside Disable
6.5 V
0.3 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. All voltages are with respect to PGND except where noted.
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ADP3121JCPZ-RL pdf
ADP3121
Rearranging Equation 1 and Equation 2 to solve for
CBST1 yields:
CBST1 + 10
QGATE
VCC * VD
CBST2 can then be found by rearranging Equation 1.
CBST2 + 10
QGATE
VGATE
*
CBST1
For example, an NTD60N02 has a total gate charge of
about 12 nC at VGATE = 7.0 V. Using VCC = 12 V and
VD = 0.1 V, then CBST1 = 12 nF and CBST2 = 6.8 nF. Good
quality ceramic capacitors should be used.
RBST is used to limit slew rate and minimize ringing at the
switch node. It also provides peak current limiting through
D1. An RBST value of 1.5 W to 2.2 W is a good choice. The
resistor needs to handle at least 250 mW due to the peak
currents that flow through it.
A small signal diode can be used for the bootstrap diode
due to the ample gate drive voltage supplied by VCC. The
bootstrap diode must have a minimum 15 V rating to
withstand the maximum supply voltage. The average
forward current can be estimated by:
IF(AVG) + QGATE fMAX
(eq. 3)
where fMAX is the maximum switching frequency of the
controller.
The peak surge current rating should be calculated by:
IF(PEAK)
+
VCC * VD
RBST
(eq. 4)
MOSFET Selection
When interfacing the ADP3121 to external MOSFETs,
the designer should consider ways to make a robust design
that minimizes stresses on both the driver and the
MOSFETs. These stresses include exceeding the short time
duration voltage ratings on the driver pins as well as the
external MOSFET.
It is also highly recommended to use the BootSnap
circuit to improve the interaction of the driver with the
characteristics of the MOSFETs. If a simple bootstrap
arrangement is used, make sure to include a proper snubber
network on the SW node.
HighSide (Control) MOSFETs
A highside, high speed MOSFET is usually selected to
minimize switching losses (see the ADP3186 or ADP3188
data sheet for FlexMode controller details). This typically
implies a low gate resistance and low input
capacitance/charge device. Yet, a significant source lead
inductance can also exist that depends mainly on the
MOSFET package; it is best to contact the MOSFET vendor
for this information.
The ADP3121 DRVH output impedance and the input
resistance of the MOSFETs determine the rate of charge
delivery to the internal capacitance of the gate. This
determines the speed at which the MOSFETs turn on and off.
However, because of potentially large currents flowing in
the MOSFETs at the on and off times (this current is usually
larger at turnoff due to ramping up of the output current in
the output inductor), the source lead inductance generates a
significant voltage when the highside MOSFETs switch
off. This creates a significant drainsource voltage spike
across the internal die of the MOSFETs and can lead to a
catastrophic avalanche. The mechanisms involved in this
avalanche condition are referenced in literature from the
MOSFET suppliers.
The MOSFET vendor should provide a rating for the
maximum voltage slew rate at drain current around which this
can be designed. Once this specification is obtained,
determine the maximum current expected in the MOSFET
by:
IMAX + IDC(per phase) ) (VCC * VOUT)
DMAX
fMAX LOUT
(eq. 5)
where:
DMAX is determined for the VR controller being used with
the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worstcase
mismatch of 30% for design margin).
LOUT is the output inductor value.
When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the
external MOSFETs as well as the PCB. However, it can be
measured to determine if it is safe. If it appears that the dV/dt
is too fast, an optional gate resistor can be added between
DRVH and the highside MOSFETs. This resistor slows
down the dV/dt, but it increases the switching losses in the
highside MOSFETs. The ADP3121 is optimally designed
with an internal drive impedance that works with most
MOSFETs to switch them efficiently, yet minimizes dV/dt.
However, some high speed MOSFETs can require this
external gate resistor depending on the currents being
switched in the MOSFET.
LowSide (Synchronous) MOSFETs
The lowside MOSFETs are usually selected to have a
low on resistance to minimize conduction losses. This
usually implies a large input gate capacitance and gate
charge. The first concern is to make sure the power delivery
from the ADP3121 DRVL does not exceed the thermal
rating of the driver (see the ADP3186, ADP3188, or
ADP3189 data sheets for FlexMode controller details).
The next concern for the lowside MOSFETs is to prevent
them from being inadvertently switched on when the
highside MOSFET turns on. This occurs due to the
draingate (Miller capacitance, also specified as Crss
capacitance) of the MOSFET. When the drain of the
lowside MOSFET is switched to VCC by the highside
turning on (at a dV/dt rate), the internal gate of the lowside
MOSFET is pulled up by an amount roughly equal to VCC
× (Crss/Ciss). It is important to make sure this does not put the
MOSFET into conduction.
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