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PDF 34AA04 Fiche technique - Microchip

Numéro de référence 34AA04
Description EEPROM
Fabricant Microchip 
Logo Microchip Logo 



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34AA04 Datasheet, Description
34AA04
4K I2CSerial EEPROM with Software Write-Protect
Device Selection Table
Part
Number
VCC Max. Clock Temp
Range Frequency Ranges
34AA04
1.7-3.6
1 MHz(1)
I, E
Note 1: 400 kHz for 1.8V VCC < 2.2V
100 kHz for VCC < 1.8V
Features
• 4 Kbit EEPROM:
- Internally organized as two 256 x 8-bit banks
- Byte or page writes (up to 16 bytes)
- Byte or sequential reads within a single bank
- Self-timed write cycle (5 ms max.)
• JEDEC® JC42.4 (EE1004-v) Serial Presence
Detect (SPD) Compliant for DRAM (DDR4)
modules
• High-Speed I2C™ Interface:
- Industry standard 1 MHz, 400 kHz, and
100 kHz
- Schmitt Trigger inputs for noise suppression
- SMBus-compatible bus time out
- Cascadable up to eight devices
• Write Protection:
- Reversible software write protection for four
individual 128-byte blocks
• Low-Power CMOS Technology:
- Voltage range: 1.7V to 3.6V
- Write current: 1.5 mA at 3.6V
- Read current: 200 µA at 3.6V, 400 kHz
- Standby current: 1 µA at 3.6V
• High Reliability:
- More than one million erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-lead PDIP, SOIC, TSSOP, TDFN, and UDFN
Packages
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description
The Microchip Technology Inc. 34AA04 is a 4 Kbit
Electrically Erasable PROM which utilizes the I2C serial
interface and is capable of operation across a broad
voltage range (1.7V to 3.6V). This device is JEDEC
JC42.4 (EE1004-v) Serial Presence Detect (SPD)
compliant and includes reversible software write
protection for each of four independent 128 x 8-bit
blocks. The device features a page write capability of
up to 16 bytes of data. Address pins allow up to eight
devices on the same bus.
The 34AA04 is available in the 8-lead PDIP, SOIC,
TSSOP, TDFN, and UDFN packages.
Package Types
PDIP/SOIC/TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
TDFN/UDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
Block Diagram
A0 A1 A2
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
HV Generator
Block 0
(000h-07Fh)
Block 1
(080h-0FFh)
Block 2
(100h-17Fh)
Block 3
(180h-1FFh)
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2014 Microchip Technology Inc.
DS20005271B-page 1
34AA04 Fiche technique
34AA04
TABLE 1-2: AC SPECIFICATIONS
AC CHARACTERISTICS
VCC = +1.7V to +3.6V
Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note
FCLK
Clock Frequency (Note 2)
10 100 kHz 1.7V VCC < 1.8V
10 400
1.8V VCC 2.2V
10 1000
2.2V VCC 3.6V
THIGH
Clock High Time
4000
600
260
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
TLOW
Clock Low Time
4700
1300
500
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
TR
SDA and SCL Rise Time (Note 1)
1000
ns 1.7V VCC < 1.8V
— 300
1.8V VCC 2.2V
— 120
2.2V VCC 3.6V
TF
SDA and SCL Fall Time (Note 1)
300 ns 1.7V VCC < 1.8V
300 1.8V VCC 2.2V
120 2.2V VCC 3.6V
THD:STA Start Condition Hold Time
4000
600
260
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
TSU:STA Start Condition Setup Time
4700
600
260
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
THD:DAT Data Input Hold Time
0 — ns (Note 3)
TSU:DAT Data Input Setup Time
250 — ns 1.7V VCC < 1.8V
100 —
1.8V VCC 2.2V
50 —
2.2V VCC 3.6V
TSU:STO Stop Condition Setup Time
4000
600
260
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
TAA
Output Valid from Clock (Note 3)
200
3450
ns 1.7V VCC < 1.8V
200 900
1.8V VCC 2.2V
— 350
2.2V VCC 3.6V
TBUF
Bus Free Time: Time the bus must
be free before a new transmission
can start
4700
1300
500
— ns 1.7V VCC < 1.8V
— 1.8V VCC 2.2V
— 2.2V VCC 3.6V
TSP Input Filter Spike Suppression
(SDA and SCL pins)
— 50 ns (Note 1)
TWC Write Cycle Time (byte or page)
5 ms —
TTIMEOUT Bus Timeout Time
25 35 ms —
— Endurance
1M — cycles Page mode, 25°C, VCC = 3.6V
(Note 4)
1: Not 100% tested.
2: The minimum clock frequency of 10 kHz is to prevent the bus timeout from occurring.
3: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
200 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2014 Microchip Technology Inc.
DS20005271B-page 3

3 Page

34AA04 pdf
34AA04
3.0 FUNCTIONAL DESCRIPTION
The 34AA04 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 34AA04
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
The 4 Kbit array of the 34AA04 is divided into two
separate banks of 2 Kbits each. The 34AA04 also
offers reversible software write protection for each of
four 1 Kbit blocks.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in Section 9.0 “Software
Write Protection”. The master device must generate
an extra clock pulse, which is associated with this
Acknowledge bit.
Note:
The 34AA04 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (34AA04) will leave the data line
high to enable the master to generate the Stop
condition.
4.6 Bus Timeout
If SCL remains low for the time specified by TTIMEOUT,
the 34AA04 will reset the serial interface and ignore all
further communication until another Start condition is
detected (Figure 4-2). This dictates the minimum clock
speed as defined by FCLK.
DS20005271B-page 6
2014 Microchip Technology Inc.

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