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PDF 24AA1026 Fiche technique - Microchip

Numéro de référence 24AA1026
Description EEPROM
Fabricant Microchip 
Logo Microchip Logo 

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24AA1026 Datasheet, Description
24AA1026/24LC1026/24FC1026
1024K I2C Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock Temp.
Frequency Ranges
24AA1026
24LC1026
24FC1026
1.7V-5.5V
2.5V-5.5V
1.8V-5.5V
400 kHz(1)
400 kHz(2)
1 MHz(3)
I
I, E
I
Note 1: 100 kHz for VCC < 2.5V
2: 100 kHz for VCC < 4.5V (E-temp)
3: 400 kHz for VCC < 2.5V
Features
• Low-Power CMOS Technology:
- Read current 450 µA, maximum
- Standby current 5 µA, maximum
• 2-Wire Serial Interface, I2C Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• Electrostatic Discharge (ESD) Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC and SOIJ
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description
The Microchip Technology Incorporated
24AA1026/24LC1026/24FC1026 (24XX1026*) is a
128K x 8 (1024 Kbit) Serial Electrically Erasable
PROM, capable of operation across a broad voltage
range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
8-Lead PDIP
8-Lead SOIC/SOIJ
NC 1
A1 2
A2 3
VSS 4
8 VCC NC
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A1A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
VCC
VSS
XDEC
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
*24XX1026 is used in this document as a generic part
number for the 24AA1026/24LC1026/24FC1026
devices.
2011-2015 Microchip Technology Inc.
DS20002270E-page 1
24AA1026 Fiche technique
24AA1026/24LC1026/24FC1026
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max. Units
Conditions
1 FCLK Clock Frequency
— 100 kHz 1.7V VCC 2.5V
— 100 kHz 2.5V VCC 4.5V, E-temp
— 400 kHz 2.5V VCC 5.5V
— 400 kHz 1.8V VCC 2.5V (24FC1026)
— 1000 kHz 2.5V VCC 5.5V (24FC1026)
2 THIGH Clock High Time
4000
— ns 1.7V VCC 2.5V
4000
— ns 2.5V VCC 4.5V, E-temp
600 — ns 2.5V VCC 5.5V
600 — ns 1.8V VCC 2.5V (24FC1026)
500 — ns 2.5V VCC 5.5V (24FC1026)
3 TLOW Clock Low Time
4700
— ns 1.7V VCC 2.5V
4700
— ns 2.5V VCC 4.5V, E-temp
1300
— ns 2.5V VCC 5.5V
1300
— ns 1.8V VCC 2.5V (24FC1026)
500 — ns 2.5V VCC 5.5V (24FC1026)
4
TR SDA and SCL Rise Time
1000 ns 1.7V VCC 2.5V
(Note 1)
— 1000 ns 2.5V VCC 4.5V, E-temp
— 300 ns 2.5V VCC 5.5V
— 300 ns 1.8V VCC 2.5V (24FC1026)
— 300 ns 2.5V VCC 5.5V (24FC1026)
5
TF SDA and SCL Fall Time
300 ns All except 24FC1026
(Note 1)
— 100 ns 1.8V VCC 5.5V (24FC1026)
6 THD:STA Start Condition Hold Time 4000
— ns 1.7V VCC 2.5V
4000
— ns 2.5V VCC 4.5V, E-temp
600 — ns 2.5V VCC 5.5V
600 — ns 1.8V VCC 2.5V (24FC1026)
250 — ns 2.5V VCC 5.5V (24FC1026)
7 TSU:STA Start Condition Setup
Time
4700
4700
— ns 1.7V VCC 2.5V
— ns 2.5V VCC 4.5V, E-temp
600 — ns 2.5V VCC 5.5V
600 — ns 1.8V VCC 2.5V (24FC1026)
250 — ns 2.5V VCC 5.5V (24FC1026)
8 THD:DAT Data Input Hold Time
0 — ns (Note 2)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2011-2015 Microchip Technology Inc.
DS20002270E-page 3

3 Page

24AA1026 pdf
24AA1026/24LC1026/24FC1026
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
NC
A1
A2
VSS
SDA
SCL
WP
VCC
PIN FUNCTION TABLE
PDIP
SOIC
SOIJ
11
22
33
44
55
66
77
88
1
2
3
4
5
6
7
8
Function
Not Connected
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)
2.1 A1, A2 Chip Address Inputs
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
3.0 FUNCTIONAL DESCRIPTION
The 24XX1026 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1026 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an
open-drain terminal, therefore, the SDA bus requires a
pull-up resistor to VCC (typical 10 kfor 100 kHz, 2 k
for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
DS20002270E-page 6
2011-2015 Microchip Technology Inc.

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