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PDF 24LC08BH Fiche technique - Microchip

Numéro de référence 24LC08BH
Description EEPROM
Fabricant Microchip 
Logo Microchip Logo 

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24LC08BH Datasheet, Description
24AA08H/24LC08BH
8K I2CSerial EEPROM with Half-Array Write-Protect
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA08H
1.7-5.5
400 kHz(1)
24LC08BH 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation Down to 1.7V for
24AA08H Devices, 2.5V for 24LC08BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 A, max.
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array (200h-3FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
TDFN, MSOP and 5-lead SOT-23
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
*24XX08H is used in this document as a generic part
number for the 24AA08H/24LC08BH devices.
Description:
The Microchip Technology Inc. 24AA08H/24LC08BH
(24XX08H*) is an 8 Kbit Electrically Erasable PROM.
The device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 A and 1 mA,
respectively. The 24XX08H also has a page write
capability for up to 16 bytes of data. The 24XX08H is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 TDFN and MSOP packages, and
is also available in the 5-lead SOT-23 package. All
packages are RoHS compliant.
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
TDFN
SCL
Vss
SDA
1
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX08. (No
internal connections).
2008-2013 Microchip Technology Inc.
DS20002084B-page 1
24LC08BH Fiche technique
24AA08H/24LC08BH
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
1
FCLK
Clock Frequency
— 400 kHz 2.5V VCC 5.5V
— 100
1.7V VCC 2.5V (24AA08H)
2 THIGH Clock High Time
600 — ns 2.5V VCC 5.5V
4000
1.7V VCC 2.5V (24AA08H)
3 TLOW Clock Low Time
1300 — ns 2.5V VCC 5.5V
4700
1.7V VCC 2.5V (24AA08H)
4 TR
SDA and SCL Rise Time
(Note 1)
— 300 ns 2.5V VCC 5.5V
— 1000
1.7V VCC 2.5V (24AA08H)
5 TF
SDA and SCL Fall Time
— 300 ns (Note 1)
6 THD:STA Start Condition Hold Time
600 — ns 2.5V VCC 5.5V
4000
1.7V VCC 2.5V (24AA08H)
7 TSU:STA Start Condition Setup Time
600 — ns 2.5V VCC 5.5V
4700
1.7V VCC 2.5V (24AA08H)
8 THD:DAT Data Input Hold Time
0 — ns (Note 2)
9 TSU:DAT Data Input Setup Time
100 — ns 2.5V VCC 5.5V
250 —
1.7V VCC 2.5V (24AA08H)
10 TSU:STO Stop Condition Setup Time
600 — ns 2.5V VCC 5.5V
4000
1.7V VCC 2.5V (24AA08H)
11 TSU:WP WP Setup Time
600 — ns 2.5V VCC 5.5V
4000
1.7V VCC < 2.5V (24AA08H)
12 THD:WP WP Hold Time
1300 — ns 2.5V VCC 5.5V
4700
1.7V VCC < 2.5V (24AA08H)
13 TAA
Output Valid from Clock
(Note 2)
— 900 ns 2.5V VCC 5.5V
— 3500
1.7V VCC 2.5V (24AA08H)
14
TBUF
Bus free time: Time the bus
1300
ns 2.5V VCC 5.5V
must be free before a new
4700
1.7V VCC 2.5V (24AA08H)
transmission can start
15 TOF
Output Fall Time from VIH
Minimum to VIL Maximum
— 250 ns 2.5V VCC 5.5V
— 250
1.7V VCC 2.5V (24AA08H)
16 TSP
Input Filter Spike Suppression
(SDA and SCL pins)
50 ns (Notes 1 and 3)
17 TWC Write Cycle Time (byte or
page)
— 5 ms —
18 —
Endurance
1M — cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.
2008-2013 Microchip Technology Inc.
DS20002084B-page 3

3 Page

24LC08BH pdf
24AA08H/24LC08BH
3.6 Device Addressing
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte consists of a four-bit control code. For
the 24XX08H, this is set as ‘1010binary for read and
write operations. The next three bits of the control byte
are the block-select bits (B2, B1, B0). B2 is a “don’t
care” for the 24XX08H. They are used by the master
device to select which of the four 256 word-blocks of
memory are to be accessed. These bits are in effect the
three Most Significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’ a read operation is
selected. When set to ‘0’ a write operation is selected.
Following the Start condition, the 24XX08H monitors
the SDA bus, checking the device type identifier being
transmitted and, upon receiving a ‘1010code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX08H will select a read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Control Code
Read/Write Bit
Block
Select
Bits
S 1 0 1 0 x B1 B0 R/W ACK
Slave Address
Start Bit
x = “don’t care”
Acknowledge Bit
DS20002084B-page 6
2008-2013 Microchip Technology Inc.

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