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PDF 74HC08D-Q100 Fiche technique - NXP

Numéro de référence 74HC08D-Q100
Description Quad 2-input AND gate
Fabricant NXP 
Logo NXP Logo 

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74HC08D-Q100 Datasheet, Description
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
Rev. 1 — 16 July 2012
Product data sheet
1. General description
The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Complies with JEDEC standard JESD8-1A
Input levels:
For 74HC08-Q100: CMOS level
For 74HCT08-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC08D-Q100 40 C to +125 C SO14
74HCT08D-Q100
74HC08PW-Q100 40 C to +125 C TSSOP14
74HCT08PW-Q100
74HC08BQ-Q100 40 C to +125 C DHVQFN14
74HCT08BQ-Q100
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
74HC08D-Q100 Fiche technique
NXP Semiconductors
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
nB
L
H
L
H
Output
nY
L
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
-
50
65
[2] -
+7
20
20
25
50
-
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
© NXP B.V. 2012. All rights reserved.
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74HC08D-Q100 pdf
NXP Semiconductors
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
Min
CPD power dissipation per package; VI = GND to VCC
capacitance
74HCT08-Q100
tpd propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
[3]
[1]
[2]
[3]
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
-
-
-
-
-
25 C
Typ
10
14
11
7
20
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
--
- pF
24 30
--
15 19
--
36 ns
- ns
22 ns
- pF
11. Waveforms
9,
Q$ Q% LQSXW
*1'
92+
Q< RXWSXW
92/
90
W3+/
9<
W7+/
90
9;
W3/+
W7/+
Fig 6.
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
DDD
Table 8. Measurement points
Type
Input
74HC08-Q100
74HCT08-Q100
VM
0.5VCC
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
74HC_HCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
VY
0.9VCC
0.9VCC
© NXP B.V. 2012. All rights reserved.
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