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Numéro de référence NCP1612B2
Description High-Efficiency Power Factor Controller
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NCP1612B2 Datasheet, Description
NCP1612A, NCP1612B,
NCP1612A1, NCP1612A2,
NCP1612A3, NCP1612B2
Enhanced, High‐Efficiency
Power Factor Controller
The NCP1612 is designed to drive PFC boost stages based on an
innovative Current Controlled Frequency Foldback (CCFF)
method. In this mode, the circuit classically operates in Critical
conduction Mode (CrM) when the inductor current exceeds a
programmable value. When the current is below this preset level, the
NCP1612 linearly decays the frequency down to about 20 kHz when
the current is null. CCFF maximizes the efficiency at both nominal
and light load. In particular, the stand-by losses are reduced to a
minimum.
Like in FCCrM controllers, an internal circuitry allows near-unity
power factor even when the switching frequency is reduced. Housed in
a SO10 package, the circuit also incorporates the features necessary
for robust and compact PFC stages, with few external components.
General Features
Near-unity Power Factor
Critical Conduction Mode (CrM)
Current Controlled Frequency Fold-back (CCFF): Low Frequency
Operation is Forced at Low Current Levels
On-time Modulation to Maintain a Proper Current Shaping in CCFF
Mode
Skip Mode Near the Line Zero Crossing
Fast Line/Load Transient Compensation
(Dynamic Response Enhancer)
Valley Turn On
High Drive Capability: 500 mA/+800 mA
VCC Range: from 9.5 V to 35 V
Low Start-up Consumption
Six Versions: NCP1612A, B, A1, A2, A3 and B2 (see Table 1)
Line Range Detection
pfcOK Signal
This is a Pb-Free Device
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SOIC10
CASE 751BQ
MARKING DIAGRAM
10
1612x
ALYW
G
1
1612x
A
L
Y
W
G
= Specific Device Code
x = A, A1, A2, A3, B or B2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
PIN CONNECTIONS
FOVP
Feedback
Vcontrol
Vsense
FFcontrol
1
(Top View)
pfcOK
VCC
DRV
GND
CS/ZCD
ORDERING INFORMATION
See detailed ordering and shipping information on page 32 of
this data sheet.
Safety Features
Separate Pin for Fast Over-voltage Protection (FOVP)
for Redundancy
Soft Over-voltage Protection
Brown-out Detection
Soft-start for Smooth Start-up Operation
(A, A1, A2 and A3 Versions)
Over Current Limitation
Disable Protection if the Feedback is Not Connected
Thermal Shutdown
Latched Off Capability
Low Duty-cycle Operation if the Bypass Diode is
shorted
Open Ground Pin Fault Monitoring
Saturated Inductor Protection
Detailed Safety Testing Analysis
(Refer to Application Note AND9079/D)
© Semiconductor Components Industries, LLC, 2016
May, 2016 Rev. 9
1
Publication Order Number:
NCP1612/D
NCP1612B2 Fiche technique
NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2
Table 1. FIVE NCP1612 VERSIONS
Part Number
Typical UVLO
Hysteresis
Condition for
BUV Tripping
(typical threshold)
NCP1612A
1.5 V
VFOVP <76%.VREF
NCP1612A1
1.5 V
VFOVP <40%.VREF
NCP1612A2
1.5 V
VFB <76%.VREF
NCP1612A3
1.5 V
VFOVP <40%.VREF
NCP1612B
8.0 V
VFOVP <76%.VREF
NCP1612B2*
8.0 V
VFB <76%.VREF
*Please contact local sales representative for availability
Maximum
Deadtime
(typical value)
48.5 ms
48.5 ms
48.5 ms
41.5 ms
48.5 ms
48.5 ms
Condition for
Latchingoff
(typical threshold)
VpfcOK >7.5 V
VpfcOK >7.5 V
VFOVP>107%.VREF
VpfcOK >7.5 V
VpfcOK >7.5 V
VFOVP>107%.VREF
UVP2 if
VFOVP<VUVP2
YES
YES
NO
YES
YES
NO
Dynamic Re-
sponse
Enhancer (DRE)
Disabled until
pfcOK turns high
Disabled until
pfcOK turns high
Disabled until
pfcOK turns high
Disabled until
pfcOK turns high
Enabled as soon
as the circuit
turns on to
speedup the
startup phase
Enabled as soon
as the circuit
turns on to
speedup the
startup phase
Recommended Applications:
The NCP1612B and NCP1612B2 large UVLO hysteresis (6 V minimum) avoids the need for large VCC capacitors and
help shorten the startup time without the need for too dissipative startup elements in selfpowered PFC applications
(where highimpedance startup resistors are generally implemented to precharge the VCC capacitor).
The A, A1, A2 and A3 versions are preferred in applications where the circuit is fed by an external power source (from
an auxiliary power supply or from a downstream converter). Its maximum startup level (11.25 V) is set low enough so
that the circuit can be powered from a 12V voltage rail.
A2 and B2 versions are to be preferred when a signal other than a portion of the output voltage is applied to the FOVP
pin (e.g., a voltage representative of the output voltage provided by an auxiliary winding) and/or if the pfcOK pin
voltage must be able to rise up to the VCC level without latching the part. Note that with the A2 and B2 versions, the
fast OVP protection latchesoff the circuit when triggered.
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NCP1612B2 pdf
NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2
Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (continued)
(Conditions: VCC = 15 V, TJ from 40°C to +125°C, unless otherwise specified)
Symbol
Rating
GATE DRIVE
VDRVlow
DRV pin level at VCC close to VCC(off) with a 10 kW resistor to GND
VDRVhigh
DRV pin level at VCC = 35 V (RL = 33 kW, CL = 220 pF)
REGULATION BLOCK
VREF
Feedback Voltage Reference:
@ 25°C
Over the temperature range
IEA Error Amplifier Current Capability
GEA Error Amplifier Gain
VCONTROL
VCONTROL Pin Voltage:
VCONTROLMAX @ VFB = 2 V
VCONTROLMIN
@ VFB = 3 V
VOUTL/VREF Ratio (VOUT Low Detect Threshold/VREF) (guaranteed by design)
HOUTL/VREF Ratio (VOUT Low Detect Hysteresis/VREF) (guaranteed by design)
IBOOST
VCONTROL Pin Source Current when (VOUT Low Detect) is activated
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
VCS(th)
TLEB,OCP
TLEB,OVS
TOCP
VZCD(th)H
VZCD(th)L
VZCD(hyst)
RZCD/CS
VCL(pos)
IZCD(bias)
IZCD(bias)
TZCD
TSYNC
TWDG
TWDG(OS)
TTMO
IZCD(gnd)
STATIC OVP
Current Sense Voltage Reference
Over-current Protection Leading Edge Blanking Time (guaranteed by design)
“OverStress” Leading Edge Blanking Time (guaranteed by design)
Over-current Protection Delay from VCS/ZCD > VCS(th) to DRV low
(dVCS/ZCD / dt = 10 V/ms)
Zero Current Detection, VCS/ZCD rising
Zero Current Detection, VCS/ZCD falling
Hysteresis of the Zero Current Detection Comparator
VZCD(th)H over VCS(th) Ratio
CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA
Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD(th)H
Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD(th)L
(VCS/ZCD < VZCD(th)L) to (DRV high)
Minimum ZCD Pulse Width
Watch Dog Timer
Watch Dog Timer in “Overstress” Situation
Time-out Timer
Source Current for CS/ZCD pin impedance Testing
DMIN
Duty Cycle, VFB = 3 V, Vcontrol pin open
ON-TIME CONTROL
TON(LL)
TON(LL)2
TON(HL)
TON(LL)(MIN)
TON(HL)(MIN)
Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM)
On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM)
Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM)
Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization)
Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization)
Min
8.0
10
2.44
2.42
110
95.0
180
450
100
50
675
200
375
1.4
0.5
0.5
80
400
20
22.0
10.5
7.3
Typ
12
2.50
2.50
±20
220
4.5
0.5
95.5
220
500
200
100
40
750
250
500
1.5
15.6
60
110
200
800
30
250
25.0
12.5
8.5
Max
14
2.54
2.54
290
96.0
0.5
250
550
350
170
200
825
300
1.6
2.0
2.0
200
200
320
1200
50
0
29.0
14.0
9.6
200
100
Unit
V
V
V
mA
mS
V
%
%
mA
mV
ns
ns
ns
mV
mV
mV
V
mA
mA
ns
ns
ms
ms
ms
mA
%
ms
ms
ms
ns
ns
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