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G2214-208-041DFB2 Datasheet PDF - GlobespanVirata

Transceiver

Numéro de référence G2214-208-041DFB2
Description Transceiver
Fabricant GlobespanVirata 
Logo GlobespanVirata Logo 
avant-première
30 Pages
		
G2214-208-041DFB2 Datasheet

1 Page

G2214-208-041DFB2 Fiche technique
June 25, 2002
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
Architecture
The interface between the Host and the transceiver
consists of the following:
Transmission Interface (data, clock and synchronization
signals)
Control Interface (microprocessor compatible)
Diagnostic Interface
Power Interface
Loop Interface
System timing is derived from a free running oscillator
in the transceiver of the central office (CO). At the
customer premises end (CPE), the CPE derives a clock
from the received line signal and provides this clock to
the CPE transmitter.
The dual-channel chip set also supports Network
Timing Recovery (NTR) at the CO end. With this feature
enabled, the CO unit will accept a clock at 8 kHz (± 100
ppm) as an input and the STU-R will output a clock that
is phase locked to the CO clock. The NTR clock should
have a duty cycle of 45-55%. Note that this feature is
only available with an UTOPIA interface.
The DSL transceiver supports both T1 and E1 rates,
and fractional rates.
Transceiver States
The following is a list of the possible states that the DSL
transceiver can be in:
IDLE mode, where the transceiver is not attempting
to start up, pass data, or perform tests
TEST mode, where the transceiver is either in local
analog loopback or local digital loopback and is not
passing user data
STARTUP mode (SDSL only), where the trans-
ceiver is attempting a startup of the DSL connec-
tion, prior to entering DATA mode
HANDSHAKE mode (HDSL2 and SHDSL), where a
link is established between the CO unit and the
CPE unit
TRAINING mode (HDSL2 and SHDSL), where the
transceiver is attempting a startup, prior to entering
DATA mode
DATA mode, where the transceiver has started up
and trained and is capable of passing user data
Software Interface
A microprocessor interface that uses simple read/write
drivers provides direct access to the GlobespanVirata
chip set—eliminating the need for complicated register
maps and advanced programming. These drivers allow
the Host to select rates, adjust transmit power, read
signal quality, and perform a variety of other tasks
which include reporting the current operational status of
the transceiver.
To configure and control the transceiver,
GlobespanVirata provides hardware-dependent driver
examples and GlobespanVirata supplied transceiver
software modules (TSMs). The TSMs have the ability to
allow a single CPU in the Host to control multiple
transceivers. This could be a potential cost savings for
arrangements where it might be advantageous to put
multiple transceivers on one card, such as at the CO.
NOTE:
You will not need a register map of the DSP, as this
information is not required to successfully design
and implement an STU. As discussed previously,
access to the DSP is provided through hardware-
dependent I/O routines and GlobespanVirata
provided TSMs.
DO-009643-DS, Issue 2
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
3

3 Page

G2214-208-041DFB2 pdf
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
System Power Requirements
The 144-pin Dual-channel DSP/Framer chip requires +3.3V (see Table 14 on page 16 for tolerance), and the two
ILD2 chips require +3.3V (±5%) as well as +5V (±5%). Power requirements, including transceiver power
consumption, have a tolerance of ±5%. The maximum peak-to-peak ripple and noise voltage is 50 mV for all
supplies.
The transceiver obtains its power from the power feed in the Host through the power interface. Table 3, Table 4,
Table 5, and Table 7 provide power requirements for the 144-pin Dual-channel DSP.
Table 3. Typical SDSL 2B1Q System Power Consumption
Per Channel (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
144
272
400
528
784
1040
1168
1552
2064
2320
Drain Current (mA)
3.3VD
DSP & ILD2
75
105
110
115
160
170
210
235
250
280
5VA
ILD2
85
85
90
90
90
90
90
95
95
95
Power/Port
(mW)
673
772
813
830
978
1011
1143
1251
1300
1400
Table 4. Typical SDSL CAP System Power Consumption
Per Channel (DSP/Framer in a 144 TQFP)
Line Rate
(Kb/s)
144
272
400
528
784
1040
1552
2064
2320
Drain Current (mA)
3.3VD
DSP & ILD2
75
80
115
145
145
145
155
165
185
5VA
ILD2
90
90
105
115
115
115
115
120
120
Power/Port
(mW)
698
714
905
1055
1055
1055
1087
1145
1210
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-02 using 1:2 transformer
Add 30 mA at 5VA for unified designs based on
SHDSL population option G-02-2302-1006C-03
using 1:4 transformer or HDSL2 population option
G-02-2302-1006C-03 using 1:5.4 transformer
3. Transmit power: 13.5 dbm (nominal at all rates)
4. Measured during activation and data mode
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-03 using 1:4 transformer
3. Transmit power: 13.5 dbm (nominal at 2320kb/s)
4. Measured during activation and data mode
GlobespanVirata, Inc. — Proprietary
6
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

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