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74LVC2G00-Q100 Datasheet PDF - NXP


Dual 2-input NAND gate

Numéro de référence 74LVC2G00-Q100
Description Dual 2-input NAND gate
Fabricant NXP 
Logo NXP Logo 
avant-première
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74LVC2G00-Q100 Datasheet

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74LVC2G00-Q100 Fiche technique
NXP Semiconductors
74LVC2G00-Q100
Dual 2-input NAND gate
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
VCC
Pin description
Pin
1, 5
2, 6
4
7, 3
8
7. Functional description
Description
data input
data input
ground (0 V)
data output
supply voltage
Table 4.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Output
nY
H
H
H
L
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
VO output voltage
Active mode
Power-down mode
0.5
[1] 0.5
[1] 0.5
[1][2] 0.5
+6.5
+6.5
VCC + 0.5
+6.5
V
V
V
V
IIK input clamping current VI < 0 V
IOK output clamping current VO < 0 V or VO > VCC
IO output current
VO = 0 V to VCC
50 - mA
- 50 mA
- 50 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
-
100
65
[3] -
100
-
+150
300
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
74LVC2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC2G00-Q100 pdf
NXP Semiconductors
74LVC2G00-Q100
Dual 2-input NAND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd
propagation delay nA, nB to nY; see Figure 5
[2]
VCC = 1.65 V to 1.95 V
1.2 3.5 8.6
VCC = 2.3 V to 2.7 V
0.7 2.3 4.8
VCC = 2.7 V
0.7 3.0 5.6
VCC = 3.0 V to 3.6 V
0.7 2.2 4.3
VCC = 4.5 V to 5.5 V
0.5
CPD power dissipation per gate; VI = GND to VCC [3] -
capacitance
1.8 3.3
14 -
40 C to +125 C Unit
Min Max
1.2 10.8 ns
0.7 6.0 ns
0.7 7.0 ns
0.7 5.4 ns
0.5 4.2 ns
- - pF
[1] Typical values are measured at nominal VCC and at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
9,
Q$Q%LQSXW
*1'
92+
Q<RXWSXW
92/
90
W 3+/
90
W 3/+
DDH
Fig 5.
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Input (nA, nB) to output (nY) propagation delays
74LVC2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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