̶ One dual-port 24-channel central DMA Controller (XDMAC)
Low-Power Features
̶ Low-power Sleep, Wait and Backup modes, with typical power consumption down to 1.1 µA in Backup mode
̶ Ultra-low-power RTC and RTT
̶ 1 Kbyte of backup RAM (BRAM) with dedicated regulator
Peripherals
̶ One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP frames
and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Time-stamping and
IEEE802.1Qav credit-based traffic-shaping hardware support.
̶ USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints,
dedicated DMA
̶ 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
̶ Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes,
time- and event-triggered transmission
̶ Three USARTs. USART0/1/2 support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester and Modem
modes; USART1 supports LON mode.
̶ Five 2-wire UARTs with SleepWalking support
̶ Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support
̶ Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and on-
the-fly scrambling
̶ Two Serial Peripheral Interfaces (SPI)
̶ One Serial Synchronous Controller (SSC) with I2S and TDM support
̶ One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
̶ Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant
on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
̶ Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM
for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control.
̶ Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and
programmable gain stage, allowing dual sample-and-hold at up to 2 Msps. Gain and offset error autotest
feature.
̶ One 2-channel 12-bit 1 Msps Digital-to-Analog Controller (DAC) with differential and oversampling modes
̶ One Analog Comparator (ACC) with flexible input selection, selectable input hysteresis
Cryptography
̶ True Random Number Generator (TRNG)
̶ AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
̶ Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
I/O
̶ Up to 115 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and
On-die Series Resistor Termination
̶ Five Parallel Input/Output Controllers (PIO)
Voltage
̶ Single supply voltage from 1.7V to 3.6V
Packages
̶ LQFP144, 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
̶ LFBGA144, 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
̶ LQFP100, 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
̶ TFBGA100, 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
̶ LQFP64, 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm
Notes: 1. 300 MHz is at [-40°C : +105°C], 1.2V or with the internal regulator.
SAM E70 [DATASHEET]
Atmel-11296C-ATARM-SAM E70-Datasheet_19-Jun-15
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